Re: GRUB Returning Less Memory
Posted: Thu Aug 03, 2017 9:52 am
Hi,
The only other alternative would have been to shift all memory mapped PCI devices above 4 GiB. In this case a "32-bit physical addresses only" OS would still waste (e.g.) 28 GiB of RAM when there's 32 GiB of RAM installed, but (as an added bonus) it also wouldn't be able to use any memory mapped PCI device.
Also note that PAE supports "no execute" page protection (while "plain 32-bit paging" doesn't); which means that you get better security too. For disadvantages, page table entries (and page directory entries, etc) are twice as large, so PAE costs a little extra memory.
I'd also say that it's one of those things where it's easier to do it sooner (before a whole bunch of other code is added on top) and harder to do it later; which means that it's better to do it now (regardless of how long it takes to do).
Cheers,
Brendan
You shouldn't blame the original designer's of "E820" for this. When PCI was first created CPUs (80486) only supported 32-bit physical addresses, and therefore the original PCI devices had to use 32-bit physical addresses. Later (when things like PAE were introduced) it was too late - PCI devices were already using 32-bit physical addresses, so there had to be a "PCI hole".Octacone wrote:So I am actively wasting an entire GB of physical memory. Great! Such a great operating system to use.Brendan wrote:For protected mode:
- If you use "plain 32-bit paging"; you're limited to to 32-bit physical addresses (4 GiB of physical address space)
- If you use "PSE-36 paging"; you're limited to 36-bit physical addresses (64 GiB of physical address space)
- If you use PAE;
- For old CPUs there's 36-bit physical addresses (64 GiB of physical address space)
- For newer CPUs (those that support long mode) it supports the same physical address size as long mode (whatever CPUID reports, up to a maximum of 52 bits)
What drugs were the people developing E820 smoking when they were implementing that.
The only other alternative would have been to shift all memory mapped PCI devices above 4 GiB. In this case a "32-bit physical addresses only" OS would still waste (e.g.) 28 GiB of RAM when there's 32 GiB of RAM installed, but (as an added bonus) it also wouldn't be able to use any memory mapped PCI device.
Why? Typically you just need to add a few "if(PAE) { ... } else { ... }" and a little extra code in a few places (in whatever function/s you use to map and unmap pages, and in the page fault handler).Octacone wrote:I use neither of those. It would be just too much work required to implement PAE.
It should take less than 1 week to implement and debug.Octacone wrote:I do not have another 3 months to implement something that I am likely to spend another month debugging and another month bug fixing.
It's ancient stuff from over 20 years ago. Every emulator has supported it for decades.Octacone wrote:Let's hypothetically think about PAE:
- Do emulators support it? QEMU, Virtual Box, Bochs
Some CPUs (e.g. cheap Atom CPUs intended for small embedded systems) only support 32-bit physical addresses. With PAE you'd be able to access 4 GiB or more physical space (up to 4096 TiB), depending on what the CPU supports. Of course the physical address space contains more than just RAM, so the amount of RAM installed is always less than the amount of space the CPU supports.Octacone wrote:
- I can physically access 64 GB of memory.
Also note that PAE supports "no execute" page protection (while "plain 32-bit paging" doesn't); which means that you get better security too. For disadvantages, page table entries (and page directory entries, etc) are twice as large, so PAE costs a little extra memory.
This is part of why "map all RAM into kernel space" is something I consider a beginner's mistake.Octacone wrote:
- I can virtually access 4 GB of memory. Meaning 64 GB (RAM) have to be mapped to 4 GB (virtual memory).
Small pages are still 4 KiB. Large pages become 2 MiB (rather than 4 MiB).Octacone wrote:
- Pages remain 4 KB right?
For someone like me (who has experience using PAE, separates "physical memory management" from "virtual memory management", etc) it'd be about 1 day. For you, I'd add an extra 2 days learning about it (especially if you're using the "recursive mapping trick", which gets a little messy for PAE), then add a few more days for debugging (the first time there's always a bug that takes a while to figure out); and then I'd round it up to 1 week (because estimates of how long any software will take to be "done" are always wrong).Octacone wrote:[*]How much time will it take to implement.
[*]Is it easy to implement if I already have a good legacy x86 paging mechanism. (please be objective)[/list]
I'd also say that it's one of those things where it's easier to do it sooner (before a whole bunch of other code is added on top) and harder to do it later; which means that it's better to do it now (regardless of how long it takes to do).
Cheers,
Brendan