Page 3 of 3
Re: How can I impliment Paging
Posted: Sun Mar 03, 2024 12:41 pm
by nexos
Even in that case there still is a race condition as what if the CPU speculatively reads from the junk PTE? Then you just read junk data into the pipeline
Re: How can I impliment Paging
Posted: Sun Mar 03, 2024 3:23 pm
by thewrongchristian
iProgramInCpp wrote:thewrongchristian wrote:Loading in uninitialised memory into the paging structure is very dangerous
I said specifically
the last level. The memory associated with the last level (whose entry belongs in a PT on x86 32-bit) isn't associated with the paging structure, rather being actual usable memory. It doesn't matter if the TLB reads the entry associated with that page before it's mapped. In fact you don't strictly have to zero that page out at all! Sure, you will be able to read what was in that page, but you're the kernel, and when dishing out pages to user space you of course would zero them out anyway.
Of course the other levels need to be zeroed out before being inserted. I was saying that the whole time!
OK, understood, it's a difference in terminology.
When you say
the last level, I took that as meaning the last level of the paging structure (i.e. the page table,) whereas you were talking about what the paging structure points to (the destination page of the PTE mapping.)
Re: How can I impliment Paging
Posted: Sun Mar 03, 2024 8:53 pm
by Xeno
Hmmm, didn't see this thread grew...
Well thanks for all the input. I think I know how I will implement it, just havent really had time yet, got some drivers done... I am going a bit off the beaten path for my memory managment. Kernel is located at 0xFA0000000000, and quite a few other odd mapings I have chosen
But thanks for all the replies, I belive I now understand paging!
Re: How can I impliment Paging
Posted: Sun Mar 03, 2024 10:13 pm
by iProgramInCpp
nexos wrote:Even in that case there still is a race condition as what if the CPU speculatively reads from the junk PTE? Then you just read junk data into the pipeline
What junk PTE? There is no junk PTE. The last level means the actual page itself.
On 64-bit the page table layout is as follows, top to bottom:
* PML4 (pointed to by CR3)
* PML3 (pointed to by entries in the PML4)
* PML2
* PML1
* The pages themselves (pointed to by entries in the PML1,
this is the last level I was talking about)
When mapping actual pages, you don't need to zero them out because they aren't part of the page table tree that's processed using the TLB.