OSDev.org

ravi wrote:(all i do after putting the data on bus is start waiting for the fifo to be empty and device to say its not busy in the status register before i put data set2 on the bus ,,, )

What happens if you wait for the FIFO to be empty but don't wait for the controller to say it's not busy?

Do you need CS to go up before you start the next transfer?

yes tried that also,, even the FIFO empty interrupts also i getting this delay,,

yes CS need to go high again,, for the next command , otherwise it will be treated as Data of the previous command

Thanks
Ravi

I think you'll need to ask your contact at Intel. I didn't see anything relevant in the available documents.

Hello Octocontrabass

by Reading Section 22.16.7 DMA Controller Interface , in 636112,

i understand that SPI's DMA integrated controller cannot work without setting up of Main DMA controller, described in section 22.3... is my understanding right?

That's correct.

Hello Octocontrabass

i am trying to setup PCH/SIO SPI DMA for SPI1(no linked list to start with) i am not able find out the following(RDC 636722)

1) how to know what should be the handshake polarity for the source and destination register CFG_LO0

2) how to know what is the source and destination peripheral ID register CFG_HI0


thanks
Ravi

You're probably supposed to write zeroes for those, but you'd have to ask your contact at Intel to know for sure. (Maybe also ask your contact at Intel why they copied the Synopsis datasheet without any proofreading.)

SIO isn't part of PSE, so you don't need to set up PSE DMA.

yeah i am Aware SIO SPI have an integrated DMA,,

Hello Octocontrabass

i tried set them 0 but DMA did not work, let me know if you find anything missing in my test code

1) I have configured SPI for Hardware CS
2) Enabled DMA tx/rx request in SSCR1 register
3) took out DMA out of reset in RESET register
4) made a dummy array and assigned its address to SAR_LO0 and made SAR_LH0 as 0(we are 32 bitmode)
5) DAR_LO0 is set address of SSDR and high register is made 0
6) Set LO0 and HO0 to 0,, no LL
7) set src and dest transfer width as 1, and donot inc dest Addr and set SRC and dest mesg size as 4 and set mem to peripheral transfer in CTL_LO0
set block transfer as 4bytes in CTL_HI0
9) Set source, dest handshake as active low in CFG_LO0,, now zeored
10) set source ID to 0 and dest ID 1 in CFG_HI0, now zerord
11) Enabled DMA in DMACFGREG
12) enabled write enable and enabeled channels in CHENREG

..... and then nothing happens

ravi wrote: ↑Tue Jul 02, 2024 10:38 am2) Enabled DMA tx/rx request in SSCR1 register

You need two DMA channels if you enable DMA for both TX and RX, but you're only configuring one DMA channel.

ravi wrote: ↑Tue Jul 02, 2024 10:38 am12) enabled write enable and enabeled channels in CHENREG

Did you enable both channels? You only configured channel 0.

The first register for DMA channel 0 is SAR_LO0. The first register for DMA channel 1 is SAR_LO1. It looks like Intel forgot to document the rest of the registers for DMA channel 1, but I think you can find them.

you are right, Thanks

But if i configure it for only channel i.e mem to Perph,, and enable only 1 channel it should work right?

i tried only enabling DMA transfer for TX and enabled on 1 channel,, but still no output, i am wondering what else needs to be configured...

Source Address, if do we &DATA it is only offset, so i gave the address of the scratchpad register


Thanks
Ravi

ravi wrote: ↑Wed Jul 03, 2024 9:56 amBut if i configure it for only channel i.e mem to Perph,, and enable only 1 channel it should work right?

I don't know. A "real" driver would use two DMA channels, so it might not work with only one.

ravi wrote: ↑Wed Jul 03, 2024 9:56 amSource Address, if do we &DATA it is only offset, so i gave the address of the scratchpad register

If the destination address is SSDR, the source address needs to be memory. You can't set CTL_LOx.TT_FC to do peripheral-to-peripheral transfers.

oh Yeah good point(i got the address form map file),,Thanks

in your earlier you suggested me to zero out Source and destination peripheral Ids(i.e hardware hand shake interface)in CFG_Hx register ,,, why?

i am little bit confused here, about how to configure the handshake interface,,, both CFG_HI0 and CFG_HI1 cannot have same handshake interface correct?
CFG_HI0(MEM - SPI) = 0x01


CFG_HI1(SPI -> MEM) = 0x10

ravi wrote: ↑Fri Jul 05, 2024 6:43 amin your earlier you suggested me to zero out Source and destination peripheral Ids(i.e hardware hand shake interface)in CFG_Hx register ,,, why?

Because the Intel documentation is terrible and I couldn't find the Linux driver. I finally found the Linux driver, though.

ravi wrote: ↑Fri Jul 05, 2024 6:43 ami am little bit confused here, about how to configure the handshake interface,,, both CFG_HI0 and CFG_HI1 cannot have same handshake interface correct?

The Linux driver uses the same for both. It sets the source peripheral ID to 1 and the destination peripheral ID to 0.

CFG_HI0 = CFG_HI1 = 0x01

The driver was written by someone at Intel, so it probably works, although I still don't understand why.