OSDev.org

quok wrote:The 3512 is a 2 port SATA2 controller that can handle JBOD, RAID 0 and 1.

Eh, seems I was wrong, the 3512 is SATA 1.0, so SATA-150, not SATA2, as discovered at the manufacturer's webpage about the 3512: http://www.sci-worx.com/products/product.aspx?id=29

Here's the page for the 3112: http://www.sci-worx.com/products/product.aspx?id=63

It seems the main differences are the 3512 is a smaller package (to be compliant with PCI 2.3), supports ATAPI devices, and is hot pluggable.

W00t, and here's there datasheet for the 3512: http://www.sci-worx.com/docs/SiI-DS-0102-D.pdf

It looks like there's also datasheets for the following Sil storage chips:

• SiI0680A - PCI to 2 Port IDE/PATA
• SiI3114 - PCI to 4 Port SATA150
• SiI3124 - PCI/PCI-X to 4 Port SATA300
• SiI3132 - PCI Express (1x) to 2 Port SATA300
• SiI3531 - PCI Express (1x) to 1 Port SATA300
• SiI3726 - 5 Drive SATA300

That's all their currently marketed SATA-to-PATA bridges, PATA controllers, SATA controllers, and SATA Port Multipliers, but none of their RAID Storage Processors. I haven't read any of the datasheets yet (I'm downloading them all now for safekeeping), but I imagine they're all similar enough that they could easily be handled by a single driver.

I hope someone finds this helpful.

Great find and good news; it appears this isn't going to be very hard after all. It differs only slightly from what I have already produced. I don't like the way many of the BSD functions are written, so I will take some time porting my own, as I haven't but a few of them written already and need to include them. I am on page 34 of 134 of that data sheet... haha... slow reader. So far it jives quite well with what I already have and expands on what I need, I love this data sheet... I giggle inside every time I learn something new whilst envisioning what crazy new thing I will do next.. haha. Well, at any rate; for those watching this thread, I should have something for you in a couple weeks, maybe three to four, due to labor day coming up and classes. I have a quiz next Tuesday and some other crap all school related drawing neigh (can I say neigh --OK, near), so bare with me. Just a heads up; however, this time around I am not going to put as much time in showing code. The reason is because my code will be for a specific driver and ONLY that driver (for now until release), so during ALPHA-BETA, which means that my code would be much too ?proprietary?, no... *custom* to post as an example for the masses. Therefore, I will post an abstract view of the PCI Bus and how to interact with DEVICES, not a device. This includes setup and usage. I will of course offer a more broad fully working example which I believe is destined for a BSD license; we will see. Thanks again for finding that data sheet man, you definitely rock hardcore!!

Hi. Been working on this driver very slowly as school has taken up a lot of my time, but I have some free time and wanted to ask a quick question:

Does this PCI stuff work as so:

Basically, I write to Base Address 0 (primary IO address) and read the response from Base Address 5 (Memory Address), right?

Thanks