Re:can't re-enter realmode
Posted: Wed Apr 07, 2004 12:01 pm
jmp word segment:offset
like(if CS=0) then do:
You should do that to flush the queue.
like(if CS=0) then do:
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jmp word 0:real_mode
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jmp word 0:real_mode
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jmp word 0:real_mode
ld doesn't do 16-bit relocations. Now you're in a tough situation, but at least it's the good situation.ich_will wrote: ld prints out:
__shutdown.o(.text+0x1e):__shutdown.o: relocation truncated to fit: 16 .text
You're doing the right thing. The only thing is that you try to jump outside of the 16-bit realmode segment you can jump to, and LD indicates that it kicks out the upper part of the offset. If your link & load address(es) are on 64k boundaries, you are all set, but LD complains that it is still losing the top half. You can load the code to 0x0000???? where LD would not lose anything. I /THINK/ that fixes it.ich_will wrote: what should / could i do? should i convert the address of the jumpmark: real_mode, to a splittet address? Do you have a complete sample code how I can return to real mode in this situation?
http://alien.dowling.edu/~rohit/nasmdoc3.html3.2 Pseudo-Instructions
Pseudo-instructions are things which, though not real x86 machine instructions, are used in the instruction field anyway because that's the most convenient place to put them. The current pseudo-instructions are DB, DW, DD, DQ and DT, their uninitialised counterparts RESB, RESW, RESD, RESQ and REST, the INCBIN command, the EQU command, and the TIMES prefix.
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00027693929e[VGA ] unsupported io write to port 0x03d6, val=0x00
00027693941i[CPU ] BxError: instruction with op1=0xfe
00027693941i[CPU ] nnn was 4
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00027693941i[CPU ] WARNING: Encountered an unknown instruction (signalling illegal instruction):
00027707455i[CPU ] BxError: instruction with op1=0xff
00027707455i[CPU ] nnn was 7
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00033179500i[CPU ] real mode
00033179500i[CPU ] CS.d_b = 16 bit <------------------ :D
00033179500i[CPU ] SS.d_b = 32 bit
00033179500i[CPU ] | EAX=60000000 EBX=0000f9dd ECX=0000f4eb EDX=0000056a
00033179500i[CPU ] | ESP=0000e36d EBP=00000739 ESI=0000f7f5 EDI=00000660
00033179500i[CPU ] | IOPL=0 NV UP DI PL ZR NA PE NC
00033179500i[CPU ] | SEG selector base limit G D
00033179500i[CPU ] | SEG sltr(index|ti|rpl) base limit G D
00033179500i[CPU ] | DS:0010( 0002| 0| 0) 00000000 0000ffff 1 1
00033179500i[CPU ] | ES:0010( 0002| 0| 0) 00000000 0000ffff 1 1
00033179500i[CPU ] | FS:0008( 0001| 0| 0) 00000000 0000ffff 1 1
00033179500i[CPU ] | GS:0008( 0001| 0| 0) 00000000 0000ffff 1 1
00033179500i[CPU ] | SS:0010( 0002| 0| 0) 00000000 0000ffff 1 1
00033179500i[CPU ] | CS:0018( 0003| 0| 0) 00000180 0000ffff 0 0 <------- ???
00033179500i[CPU ] | EIP=00007213 (00007213)
00033179500i[CPU ] | CR0=0x60000010 CR1=0x00000000 CR2=0x00000000
00033179500i[CPU ] | CR3=0x00000000 CR4=0x00000000
00033179500i[ ] restoring default signal behavior
00033179500i[CTRL ] quit_sim called with exit code 1