Wants the RTC to interrupt 1024/s...

[Ozguxxx]

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But why only the 5 lower bits and not 7? 

Hey thats a good question... ;D But I can only answer second part. Why not 7 bits? Well, since cmos ram only supplies 64 bytes of info, you do not need 7 bits, 6 bits are enough however, all the sources says that only least significant 5 bits of port 0x70 should be used and other bits should be leaved untouched. But in fact 5 bits are not enough to index 64 bytes. I am also confused. So thats the only help I can give for now.

[Peter_Vigren]

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But why only the 5 lower bits and not 7? 

Hey thats a good question... ;D But I can only answer second part. Why not 7 bits? Well, since cmos ram only supplies 64 bytes of info, you do not need 7 bits, 6 bits are enough however, all the sources says that only least significant 5 bits of port 0x70 should be used and other bits should be leaved untouched. But in fact 5 bits are not enough to index 64 bytes. I am also confused. So thats the only help I can give for now.

Not all All sources... HelpPC say that bit 7 and 6 should be left untouched and bit 7 controls the NMI...

[Ozguxxx]

I meant all the sources I checked I think I have mistyped it ;D... I think you are right I was also confused but in indispensable pc hardware book and in xavier's web site it is done in the way which uses only least significant 5 bits. But helppc says in other way. Can gurus or anybody who is REALLY aware of this stuff help us? Thanx...

[Peter_Vigren]

I meant all the sources I checked I think I have mistyped it ;D... I think you are right I was also confused but in indispensable pc hardware book and in xavier's web site it is done in the way which uses only least significant 5 bits. But helppc says in other way. Can gurus or anybody who is REALLY aware of this stuff help us? Thanx...

The most logical would be that HelpPC is correct. As you yourself stated, all 64 registers can not be accessed using only 5 bits.

[Therx]

I wasn't aware of having to save the top two bits of 0x70 so I just write the address to the port. This has no obvious problems I've experienced

[Peter_Vigren]

I wasn't aware of having to save the top two bits of 0x70 so I just write the address to the port. This has no obvious problems I've experienced

If bit 7 is zero, NMI is disabled. And because it is disabled, you will not experience any NMI-interrupt if it would occur and then it is quite understandable that you haven't had any problems with it

[Therx]

NMI - Non Maskable Interrupt. I thought you couldn't mask these. But aren't all exceptions up to 13h or whatever NMIs. Unfortunally I still get these

[Pype.Clicker]

You can mask NMI trough port 0x70, but not through IF in eflags, so for a CPU point of view, they aren't maskable -- that's where the name come from (before that port 0x70 was defined).

Exceptions can't be masked, neither with CLI, nor with port 0x70. And there are no reason why NMI could mask it as they are *not* hardware interrupt requests, but internal-raised signals.

You can view the NMI feature as a logic gate that would read the 7th bit of some BIOS register (mapped to IO-port 0x70) and force the IRQ2 (iirc) line to be inactive (never raises an interrupt). Therefore, it couldn't affect the internal CPU exceptions ...