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Octocontrabass wrote:We need to see your code to answer that question.

__attribute__ ((interrupt)) void sched_time_handler(struct interrupt_frame* frame) {
    static uint8_t time_passed = 0;
    time_passed += 10;

    prepare_rt_tasks();
    if (time_passed >= STD_TIMESLICE) {
        resched();
        time_passed = 0;
    }

    send_eoi(0);
}

KrotovOSdev wrote:

Octocontrabass wrote:We need to see your code to answer that question.

Here it is:

Code: Select all

__attribute__ ((interrupt)) void sched_time_handler(struct interrupt_frame* frame) {
    static uint8_t time_passed = 0;
    time_passed += 10;

    prepare_rt_tasks();
    if (time_passed >= STD_TIMESLICE) {
        resched();
        time_passed = 0;
    }

    send_eoi(0);
}

thewrongchristian wrote:

KrotovOSdev wrote:

Octocontrabass wrote:We need to see your code to answer that question.

Here it is:

Code: Select all

__attribute__ ((interrupt)) void sched_time_handler(struct interrupt_frame* frame) {
    static uint8_t time_passed = 0;
    time_passed += 10;

    prepare_rt_tasks();
    if (time_passed >= STD_TIMESLICE) {
        resched();
        time_passed = 0;
    }

    send_eoi(0);
}

When you pre-empt your current process, you call resched() before you send EOI to the PIC. So you'll never get another timer interrupt (or any other IRQ interrupt, for that matter) until the original process is scheduled again somehow.

Octocontrabass wrote:Without seeing the rest of your code, it's hard to say what could be the problem there.

//irq.c 
void set_idt_entry(void (*irq_handler), uint8_t entry) {
    uintptr_t irq_handler_address = (uintptr_t)irq_handler;

    idt[entry].offset_low = (uint16_t)(irq_handler_address & 0xFFFF);
    idt[entry].selector = 0x08;  // Селектор сегмента кода
    idt[entry].zero = 0;
    idt[entry].flags = entry < 0x20 ? 0x8F : 0x8E;
    idt[entry].offset_high = (uint16_t)((irq_handler_address >> 16) & 0xFFFF);
}

void load_idt() {
    struct {
        uint16_t idt_size;
        uint32_t idt_address;
    } __attribute__((packed)) idt_t;

    idt_t.idt_size = sizeof(idt_entry_t) * 256 - 1;
    idt_t.idt_address = (unsigned long)idt;

    asm volatile ("lidt %0" : : "m" (idt_t));

    return;
}

//timer.c
__attribute__ ((interrupt)) void sched_time_handler(struct interrupt_frame* frame) {
    static uint8_t time_passed = 0;
    time_passed += 10;

    prepare_rt_tasks();

    send_eoi(0);
    if (time_passed >= STD_TIMESLICE) {
        resched();
        time_passed = 0;
    }
}

//sched.c
struct TaskStruct* now_executed;

void resched() {
    asm volatile("sti");

    scheduler_queue_t* task;

    for (uint8_t i = 255; i >= 0; i--) {
        if (scheduler.queue_task_count[i] == 0) continue;
        task = scheduler.scheduler_queues[i];

        do {
            if (task->task.state == TASK_STATE_WAITING || task->task.state == TASK_STATE_RUNNING) {
                task->task.state = TASK_STATE_RUNNING;
                now_executed->state = TASK_STATE_WAITING;

                switch_context(&(task->task));
                return;
            }

            task = task->next_task_queue;
        } while (task != scheduler.scheduler_queues[i]);
    }

    asm volatile("cli");
}

//task_switch.asm
extern now_executed
extern TSS
global switch_context

switch_context:
    push ebx
    push esi
    push edi
    push ebp
 
    mov edi,[now_executed]    ;edi = address of the previous task's "thread control block"
    mov [edi + TCB.esp],esp         ;Save ESP for previous task's kernel stack in the thread's TCB
 
    ;Load next task's state
 
    mov esi,[esp+(4+1)*4]         ;esi = address of the next task's "thread control block" (parameter passed on stack)
    mov [now_executed],esi    ;Current task's TCB is the next task TCB
 
    mov esp,[esi + TCB.esp]         ;Load ESP for next task's kernel stack from the thread's TCB
    mov eax,[esi + TCB.pgd]         ;eax = address of page directory for next task
    mov ebx,[esi + TCB.esp0]        ;ebx = address for the top of the next task's kernel stack
    mov [TSS + TSS_struc.esp0],ebx   ;Adjust the ESP0 field in the TSS (used by CPU for for CPL=3 -> CPL=0 privilege level changes)
    mov ecx,cr3                   ;ecx = previous task's virtual address space
 
    cmp eax,ecx                   ;Does the virtual address space need to being changed?
    je .doneVAS                   ; no, virtual address space is the same, so don't reload it and cause TLB flushes
    mov cr3,eax                   ; yes, load the next task's virtual address space
.doneVAS:
    pop ebp
    pop edi
    pop esi
    pop ebx
 
    ret                           ;Load next task's EIP from its kernel stack

rdos wrote:In my experience, after having rewritten the scheduler several times due to poor design, you should separate saving thread state from loading thread state. You should also save ALL registers in your TCB, not just some. Register context should not be saved on the (interrupt) stack as this is begging for problems later when voluntary context switches are added. While the scheduler decides which thread to run next, it should run on a private (per-core) kernel stack. The scheduler should be designed in two parts: The part that handles real-time events, and the part that does load balancing and moving threads between cores.

You also need to design some method so IRQs can wakeup threads, something that complicates things a lot, but which is necessary.

KrotovOSdev wrote:

rdos wrote:In my experience, after having rewritten the scheduler several times due to poor design, you should separate saving thread state from loading thread state. You should also save ALL registers in your TCB, not just some. Register context should not be saved on the (interrupt) stack as this is begging for problems later when voluntary context switches are added. While the scheduler decides which thread to run next, it should run on a private (per-core) kernel stack. The scheduler should be designed in two parts: The part that handles real-time events, and the part that does load balancing and moving threads between cores.

You also need to design some method so IRQs can wakeup threads, something that complicates things a lot, but which is necessary.

IRQ can wakeup thread by setting its state to Waiting in my case but it's not implemented yet.
Do you mean that I have not to use kernel interrupt stack for saving registers? Then do I have to use task stack for saving them?

rdos wrote:

KrotovOSdev wrote:That took more time than it should but here is my code

    idt[entry].flags = entry < 0x20 ? 0x8F : 0x8E;

__attribute__ ((interrupt)) void sched_time_handler(struct interrupt_frame* frame) {

    asm volatile("sti");
    asm volatile("cli");

    mov eax,[esi + TCB.pgd]         ;eax = address of page directory for next task
    mov ebx,[esi + TCB.esp0]        ;ebx = address for the top of the next task's kernel stack
    mov [TSS + TSS_struc.esp0],ebx   ;Adjust the ESP0 field in the TSS (used by CPU for for CPL=3 -> CPL=0 privilege level changes)
    mov ecx,cr3                   ;ecx = previous task's virtual address space
 
    cmp eax,ecx                   ;Does the virtual address space need to being changed?
    je .doneVAS                   ; no, virtual address space is the same, so don't reload it and cause TLB flushes
    mov cr3,eax                   ; yes, load the next task's virtual address space
.doneVAS:

rdos wrote:You should also save ALL registers in your TCB, not just some. Register context should not be saved on the (interrupt) stack as this is begging for problems later when voluntary context switches are added.

Octocontrabass wrote: Where's the rest of your code?

Octocontrabass wrote: Are you sure you want interrupts to remain enabled when an exception occurs? Usually you need to make sure the CPU is in a consistent state in your exception handler before you can enable interrupts.

Octocontrabass wrote: You need to write interrupt handler entry points in assembly, especially if you want to nest interrupts.

__attribute__ ((interrupt))

Octocontrabass wrote: This part doesn't need to be written in assembly.

KrotovOSdev wrote:I can send it here but it's quite long so I think I shouldn't post it here, should I?

KrotovOSdev wrote:Does it mean that I shouldn't use Trap gate for exception handler? Or what do I have to do to make CPU's state consistent.

KrotovOSdev wrote:What's the problem with

Code: Select all

__attribute__ ((interrupt))

and how can that stop me from adding nested interrupts? I've also swapped "sti" and "cli" (what a dumb mistake...).

nullplan wrote:For the first: No. Always use interrupt gates. I don't know what the point of trap gates is, but I see no point in them. Typically it is better to have the CPU disable the interrupt flag, then look at the situation in your interrupt entry code and decide from that whether to re-enable it. This precludes any possibility of a stack overflow if the interrupts are coming too quickly.

nullplan wrote:The attribute is GCC specific and quite underdocumented. I have no idea how the thing is supposed to work on x86, how it can tell between exceptions with error code and those without (do you have to make two different types of register struct?), and how I can get at user registers. I really need to do that for system calls and user space exceptions. These are all uncertainties I don't need in my life, so I just write the thing in assembler, where I can set the rules.

nullplan wrote:For the nested interrupts: You need to ensure that you have "enough" space left on stack before re-enabling interrupts, which is easy in assembler, but not so easy in C. Maybe that's what Octo meant.