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Well, it seems that Bios uses fragments to realize larger screens, which was possibly expected. I just wonder how that works with the legacy VESA driver and operating systems on top. While Win98 will probably just run in real mode and use the fragmented memory setup, I wonder what that means for VESA drivers of later systems that run in protected mode. from my naive understanding, it would mean that the native VESA driver would then simply fail.

Maybe that is good enough - to have a failsafe fallback for installation, and run in enhanced mode all the way once the Os switches to the protected mode. Who would miss the legacy VGA modes anyhow...

Concerning the interrupt wierdos, I am possibly one step further. While the documentation states that one can access the chip registers either through the I/O ports, or in memory-mapped mode, this does not seem to be generally true. The CRTC/GRT etc ports are always available as I/O ports. Howerver, if my current finding is correct, INPUTSTATUS0 is different. If the chip operates in enhanced mode, it is only available as memory mapped register, and the I/O port returns zero. However, beware if you attempt to read the memory mapped register from non-enhanced VGA modes like planar - then the chip hangs. I suspect that it does a PCI disconnect.

Thus, unlike documented, the availability of MMIO or I/O ports is mode-dependent.

The MMIO register for IRQ also works differently than documented. First, any attempt to read it as 32-bit port clears the lower 16 bits. If only the 16 LSBs are read, the register does return non-zero results, but also differently than documented. You first have to clear the interrupt by writing a 1 bit (that is documented), but you need to write again a zero to make the register ready to indicate an interrupt detection in the next round, otherwise the bit sticks to 1, making it impossible to register any interrupt reliably.

All I can say that the documation of this chip is quite sloppy.

thorfdbg wrote:While Win98 will probably just run in real mode and use the fragmented memory setup, I wonder what that means for VESA drivers of later systems that run in protected mode.

Protected mode operating systems with VBE drivers (including Windows 98) use virtual 8086 mode to call the functions to set the mode. If the ROM supports it, they'll request a linear frame buffer. Otherwise, they'll use virtual 8086 mode to call the display window control function to access different parts of the frame buffer.

thorfdbg wrote:All I can say that the documation of this chip is quite sloppy.

They probably didn't expect anyone to write their own driver without using the ROM.

Just in the S3 manual again, and there are two settings which I do not quite understand. Maybe someone knows a bit more about what they mean.

In the CR31 register (memory configuration), the description of bit 2 says:

Bit 2 VGA 16B - Enable VGA 16-bit Memory Bus Width
o = 8-bit memory bus operation
1 = Enable 16-bit bus VGA memory read/writes
This is useful in VGA text modes when VGA graphics controller functions are typically not used.

From the chip description, the memory bus is always 32 bit wide, but even if we could switch the bus width, why is that "useful in VGA text modes". I would believe a wider bus is always of advantage, so why cut it shorter by default? Setting or clearing this bit makes no observable difference in graphics modes. The rest of the manual does not (as expected) tell anything about the usage of this bit.

There is also another bit:

Bit 6 HST OFF - Enable High Speed Text Display Font Fetch Mode
o = Normal font access mode
1 = Enable high speed text display
Setting this bit to 1 is only required for DCLK rates greater than 40 MHz. See bit 5 of CR3A.

Bit 5 of CR3A mentions:

Bit 5 HST DFW - Enable High Speed Text Font Writing
o = Disable high speed text font writing
1 = Enable high speed text font writing
Setting this bit to 1 is only required for DCLK rates greater than 40 MHz. See bit 6 of CR31.

Bit 6 CR31 makes again no observable difference, pbably because I'm not in a text mode. But even if I would, what does "high-speed" mean? Higher pixel clock? Setting bit 5 of CR3a does make a difference - graphics is corrupted, by some pixel noise. So apparently, it is "too fast" for something in the chip.

But again, why is this setting "required" for some DCLK rates, and why would one then *not* set this bit? In practice, you cannot set CR3A bit 5, though the manual does not state under which conditions *not* to set it.

For the record, the VBios does set bit 2 of CR31 (16 bit VGA memory bus), it does not set the high-speed text fetch bit (bit 6 CR31).

(This seems all an example of "how not to write technical specs", but I'm a bit late for this complaint, I afraid.)

Enable VGA 16-bit Memory Bus Width

In graphical modes, the VGA graphics controller processes data byte-by-byte, using latches. VGA use outside 8-bit wide data bus.
In text modes, no latch registers are used.

Enable High Speed Text Display Font Fetch Mode
Enable High Speed Text Font Writing

Setting this bit to 1 is only required for DCLK rates greater than 40 MHz

Perhaps this is for extended text modes 132x25 or 132x43.

vga wrote:

Enable VGA 16-bit Memory Bus Width

In graphical modes, the VGA graphics controller processes data byte-by-byte, using latches. VGA use outside 8-bit wide data bus.
In text modes, no latch registers are used.

Yes, the latches for the GDC modes. No use for them in the text mode. However, why would you need to explicitly disable them (isn't that done by switching to text mode anyhow?)

No, the VBios does not set this bit.

thorfdbg wrote:Found it! The solution of this riddle is an innocent looking bit in one of the clock control registers of the CRTC that reduces the memory access cycle count from 3 to 2. The additional cycle is required to perform the VGA "address bit shuffle"

What the index of the register?

For planar mode:
CR14 bits 5, 6 must be reset
CR17 bit 3 must be reset
CR17 bit 6 must be set
CR31 bit 3 must be reset
CR3A bit 4 must be reset
CR43 bit 3 must be reset

CRT controller must work in byte mode.

CPU memory mapping mode must be "unchained".

128K display memory available - odd/even memory mapping mode activated?

vga wrote: What the index of the register?

None of the above. It is SR15 bit 7. I said it looks fairly innocent, but with the bit set, the graphics controller is not used and bypassed completely.