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It's quite simple. As Intel say in their Programmer's Manual:

The memory that the processor addresses on its bus is called physical memory. Physical memory is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address.

Forget your right-hand diagram.

iansjack wrote:It's quite simple. As Intel say in their Programmer's Manual:

The memory that the processor addresses on its bus is called physical memory. Physical memory is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address.

Forget your right-hand diagram.

Okay, but then why would be the width of the data bus 16/32/64 bits?

The data bus is irrelevant in this context. It only determines how many of those 8-bit bytes the processor can access simultaneously. In the case of a processor with a 64-bit data bus that would be 1, 2, 4, or 8.

iansjack wrote:The data bus is irrelevant in this context. It only determines how many of those 8-bit bytes the processor can access simultaneously. In the case of a processor with a 64-bit data bus that would be 1, 2, 4, or 8.

It's not irrelevant since it can store for example, 64 bits at the same address due to the width of the memory and I know by looking at the 8086 specification which tells me that it acts exactly the way I described but it can store just 16 bits at single address. And also by looking at the sample 8086 computer whose schematic I added as attachment, you can see that it has memory which is 16 bits wide ( by looking at one of the four memories located at the upper left corner you can see one acting as the higher 8 bits and the another one as the lower 8 bits at the same address ).

The memory layout of the 8086 and 8088 are identical. Each byte is separately addressed, not each word.

The advantage of having a 16-bit address bus is as follows:

• If you perform an 8-bit memory read/write on an 8086 and 8088 of the same clock speed, they will both take roughly the same amount of time, but on the 8086 you're only using half the data bus.
• If you perform a 16-bit read/write on the 8086 and 8088, the 8088 will take roughly twice as long. This is because the 8086 can perform the entire read/write in a single bus cycle, while the 8088 has to do it in two cycles.

Note this also affects code execution, since very few instructions are only 1 byte long, 2 bytes is most common. Worse, the 8086 has a 6 byte prefetch queue (a place to load the next instruction while the current one is running) while the 8088 only had 4 bytes. Therefore the 8086 can often run 3 instructions without having to read from RAM while the 8088 can usually only do 2. Furthermore, neither CPU could prefetch while running an instruction that used RAM, since prefetches (typically) took twice as long on the 8088, the prefetch queue would run out much more often. Ultimately, all this makes the 8086 substantially more than twice as fast as the 8088 at the same clock speed. Improvements of 5x for certain workloads are not uncommon. The Commodore 64's 1Mhz 6502 was often faster for real-life applications than the original PC's 4.77Mhz 8088.

Basically it comes down to performance vs. price of RAM chips and the complexity of the motherboard. From a programmer perspective, both CPUs act exactly the same.

lukassevc wrote:

iansjack wrote:The data bus is irrelevant in this context. It only determines how many of those 8-bit bytes the processor can access simultaneously. In the case of a processor with a 64-bit data bus that would be 1, 2, 4, or 8.

It's not irrelevant since it can store for example, 64 bits at the same address due to the width of the memory

A memory address can only hold 8 bits, the width of the data bus has nothing to do with it. This was true with the 8086, 8088 and is still true with modern 64 bits processors and is not going to change.

The processor cannot store 64 bits at a single address. It stores them at 8 consecutive addresses. It would make no sense to think of memory as an array of 64-bit elements as that woul make access to single bytes difficult.

You can believe Intel's description that I quoted earlier.

Okay, if the CPU can only access 8-bits at a single address, why its data bus is 64 bits wide as on the attached pinout image ( in this case it's the Core 2 )?

So that this CPU can read or write to 8 consecutive addresses at the same time.

Nobody ever said it could only access 8 bits at once. I specifically said it can access 1, 2, 4, or 8 bytes at the same time. That's 8 bytes at 8 consecutive addresses.

You are confusing the hardware implementation with the instruction set. They do not reflect each other as directly as that. In many ways, the ISA is itself a layer of abstraction over the physical hardware.

Furthermore, the pinout to memory isn't a particularly good measure of the memory access in 32-bit and 64-bit x86 CPUs, as all of them cache memory accesses on-chip anyway - the physical address bus is mainly used to fill cache lines when a cache miss occurs, and the fills usually involve at least 32 bytes at once in the oldest such CPUs, and a lot more on modern ones (I don't know exact figures, but from the system programmer's POV it doesn't really matter much). A modern processor will rarely if ever access uncached memory directly.

But that's beside the point; the point is that the system word is the most which can be fetched at a single go, but it doesn't change the fact that addresses are byte-wise.

lukassevc wrote:And also by looking at the sample 8086 computer whose schematic I added as attachment, you can see that it has memory which is 16 bits wide ( by looking at one of the four memories located at the upper left corner you can see one acting as the higher 8 bits and the another one as the lower 8 bits at the same address ).

That's a nice schematic. Look closely at how the address bus is attached to each of those 8-bit memories. Notice how A0 isn't connected to them? Instead, A0 is combined with /BHE to choose which of the two memories is enabled. This allows the CPU to choose a specific byte instead of only addressing words.

Okay, I think I finally understand what you were trying to tell me the whole time, so for an example image we are saving 0x1234 to the memory address 0x00000, it spits out the address and pulls /BHE low, then it puts 0x0034 to the 16-bits wide data bus, then it pulls /BHE high and spits 0x1200 to the data bus, the /BHE signal is essentially the A0 ( later signals /B0 to /B7 represent decoded address lines A0 to A2) , am I correct? The attached image explains this, the according bank/i.e. the according 8-bits of the whole data bus are selected using the /Bn signals. And if so, the last question the HDD most likely saves to each address one byte from the loaded 512 bytes, right? Also, when I, for example, do mov eax, [0x1234, then the lowest 8-bits are from address 0x1234, the seconds left-most 8-bits are from the address 0x1235, the third left-most 8-bits are from the address 0x1236 and the forth left-most 8-bits are from the address 0x1237, i.e. eax=[0x1237][0x1236][0x1235][0x1234], what basically means that the address in square bracelets represents the corresponding 8-bits, right?

lukassevc wrote:Okay, I think I finally understand what you were trying to tell me the whole time, so for an example image we are saving 0x1234 to the memory address 0x00000, it spits out the address and pulls /BHE low, then it puts 0x0034 to the 16-bits wide data bus, then it pulls /BHE high and spits 0x1200 to the data bus, the /BHE signal is essentially the A0 ( later signals /B0 to /B7 represent decoded address lines A0 to A2) , am I correct?

Not quite. If you're writing a word to a word-aligned address, the CPU will write the entire word in one cycle. The CPU will pull both A0 and /BHE low to indicate it's accessing both bytes of the word, then put 0x1234 on the data bus. (A0 and /BHE are similar to /B0 and /B1 in newer processors.)

If the CPU is only accessing one byte in a word, then it will pull A0 low if it's accessing the byte at the even address, or it will pull /BHE low if it's accessing the byte at the odd address. To write a word at an odd (not aligned) address, the CPU will split it into two bytes and use two cycles.

lukassevc wrote:The attached image explains this, the according bank/i.e. the according 8-bits of the whole data bus are selected using the /Bn signals. And if so, the last question the HDD most likely saves to each address one byte from the loaded 512 bytes, right?

Right.

lukassevc wrote:Also, when I, for example, do mov eax, [0x1234, then the lowest 8-bits are from address 0x1234, the seconds left-most 8-bits are from the address 0x1235, the third left-most 8-bits are from the address 0x1236 and the forth left-most 8-bits are from the address 0x1237, i.e. eax=[0x1237][0x1236][0x1235][0x1234], what basically means that the address in square bracelets represents the corresponding 8-bits, right?

Right.

Not quite. If you're writing a word to a word-aligned address, the CPU will write the entire word in one cycle. The CPU will pull both A0 and /BHE low to indicate it's accessing both bytes of the word, then put 0x1234 on the data bus. (A0 and /BHE are similar to /B0 and /B1 in newer processors.)

If the CPU is only accessing one byte in a word, then it will pull A0 low if it's accessing the byte at the even address, or it will pull /BHE low if it's accessing the byte at the odd address. To write a word at an odd (not aligned) address, the CPU will split it into two bytes and use two cycles.(A0 and /BHE are similar to /B0 and /B1 in newer processors.)

Ah okay, okay, thank you very much for you explanation, now it's way more clear!