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. Maybe BIOS emulates the USB as ATA??Nope. If you want to access USB without using INT 0x13, you need USB drivers.sunnysideup wrote:Maybe BIOS emulates the USB as ATA??
5. I've programmed the timer (that corresponds to port numbers 0x40 and 0x43). Where is this located?Quote:
What the original IDE specification did was to detach the disk controller boards from the motherboard, and stick one controller onto each disk drive, permanently. When the CPU accessed a disk IO port, there was a chip that shorted the CPU's IO bus pins directly onto the IDE cable -- so the CPU could directly access the drive's controller board. The data transfer mechanism between the CPU and the controller board remained the same, and is now called PIO mode. (Nowadays, the disk controller chips just copy the electrical signals between the IO port bus and the IDE cable, until the drive goes into some other mode than PIO.)
Quoted from the wiki ^
So are disk controllers present in the disk drives? Is it the same today?
Quote:
Current disk controller chips almost always support two ATA buses per chip
Are these the same disk controllers that are present in the disk drives? What does it mean that it supports 2 buses per chip? I thought there should be 2 chips per bus (2 disk drives per bus : master/slave and if each disk has a controller, 2 chips per bus)
. These were just of the top of my head. Maybe I'll find more XD. I'm just curious tbh.The only logical view you can have on the motherboard is the one presented to the CPU. And it is this: The CPU is directly connected to some memory. Ask BIOS (Int 15h, Function E820) or UEFI for how much and where it is. It is also directly connected to some peripherals in address space. Ask ACPI and the PCI bus about where and what. Other than the ISA devices (which are all the legacy devices like PIT, PIC, ISA DMA controller, etc., and, of course, the PCI controller), you find all your hardware on the PCI bus like it was 1995. Only difference now is, if you can support it, you can talk to PCI config space using MMIO. Ask ACPI about details.sunnysideup wrote:0. Can most of today's motherboards be "logically" considered as this?
Depends, but it is unlikely you would notice until you're getting quite deep into the architecture of things. And right now you don't even have USB driverssunnysideup wrote:1. The first issue that I see with this picture is that it isn't multiprocessing. If it were, how would the diagram vary?
. There were multi-socket main boards (and they still exist and are used for servers and stuff), in which multiple CPUs (multiple physical packages) would be slotted into different sockets, often each with their own memory attached. All CPUs could still see all memory, but accessing non-local memory would require requests to be routed across the MB and thus take longer (the North Bridges would handle that, no need for software support). It is therefore advantageous to allocate memory for a CPU in the memory closest to the CPU. Such an architecture is called NUMA. These days you usually have SMP systems, in which there is only one CPU package containing multiple cores, often multiple threads in those cores. But all memory is still accessed locally, so unless there is cache contention, all memory accesses take the same time. Such an architecture is called UMA.The ISA bus is what the PC clone industry called the PC standard. It still exists. Your PCI bus will have an ISA gateway somewhere, and reading about ICHs and PCHs you might come across a thing called the LPC bus, which is just the ISA bus with fewer pins. Instead of running with 32 pins at 4MHz, they are running with 4 pins at 32MHz, but the throughput is the same. I'm oversimplifying here, obviously, but you were not making hardware for the thing, you were just looking to program it.sunnysideup wrote:2. I know that OLD (very very old PCs) used something called an ISA bus. Has it been replaced? Has it been removed? Is there a bus with similar functionality in today's motherboards?
The IOAPIC is inside the South Bridge (low speed device). The LAPIC is inside the CPU (in each thread, really).sunnysideup wrote:3. Where would the IOAPIC and the LAPIC be located on this board?
Motherboard. MB ATA controller talks to the Integrated Disk Electronics on the drive in a standard way, but that is one step removed from the CPU. The CPU only talks to the ATA controller, and then that thing works some black magic you neither know nor care about, and then your sector appears in memory somewhere.sunnysideup wrote:4. Is the ATA controller present in the disk drive or on the motherboard?
Inside the South Bridge. As is most legacy hardware. Even the RTC.sunnysideup wrote:5. I've programmed the timer (that corresponds to port numbers 0x40 and 0x43). Where is this located?
What does it matter to you? You talk to a PCI device, say a RAID controller, then it does something, and then another hard disk sector appears in memory. You don't need to talk to the PCI device any more than that, and you don't need to setup the DMA transfer like you needed with ISA, so how exactly those bytes get from the disk into the memory is something you don't have to care about.sunnysideup wrote:6. Is the PCI controller (busmaster?) located in the southbridge (ICH)?
I dual-boot my test machine. One of the OSs on it has a suitable network driver and Unix-like device files. In that OS, I can use netcat to write straight from the network to a disk partition. To send the data from a Unix box, I also use netcat. (To be exact, I don't actually use netcat because none of my OSs are actually Unixes at present, but that's probably irellevant detail. The things I do use happily interoperate with netcat; they all just listen for or open TCP streams.)Octocontrabass wrote:Nope. If you want to access USB without using INT 0x13, you need USB drivers.sunnysideup wrote:Maybe BIOS emulates the USB as ATA??
