OSDev.org

jacks wrote:

Owen wrote:Correct, providing the cache settings of all CPUs are set correctly (i.e. if one processor has a block of physical memory UC and another WB, then bad things will happen), and noting some oddities surrounding the write combining cache setting.

Are these cache settings for CPUs set by MCH/Northbridge or BIOS has something to do with these at power on?.

They're found in the MTRRs, which are well documented in the Intel/AMD manuals. The BIOS will normally set them correctly; sometimes, the OS might want to tweak them for extra performance (normally making the video framebuffer write combining in the MTRR; slightly more effficient than doing so with just the page tables); whether this can be done depends upon if the BIOS used all the MTRRs.

The MTRRs need to have the same setting on all cores.

Owen wrote: They're found in the MTRRs, which are well documented in the Intel/AMD manuals. The BIOS will normally set them correctly; sometimes, the OS might want to tweak them for extra performance (normally making the video framebuffer write combining in the MTRR; slightly more effficient than doing so with just the page tables); whether this can be done depends upon if the BIOS used all the MTRRs.

The MTRRs need to have the same setting on all cores.

Thanks Owen, now that becomes clear.