Combuster wrote:And then there's the stuff like APIC timers, non-PIC interrupt controllers and message-signalled interrupts that push the limit much further if you want.
I see. Didn't know about those. Anyway, that's for the future. I think the next thing in my list is physical memory management. I'll try not to rely on tutorials this time, as this is simply working with the memory, no chip programming involved, since I'm not looking into paging.
Anyway, this might go a little bit of topic, but I had a question about hlt unanswered. Let me illustrate first.
let's say I have code like this and the kernel entry point is entry().
Code: Select all
entry:
call initidt
call initpit
hang:
hlt
int 1
jmp hang
And I get output like this.
tick: 1
received interrupt: 1
tick: 2
received interrupt: 1
tick: 3
received interrupt: 1
...
It seems, that when an interrupt is fired from the PIT, the processor resumes from where it left off when it executed hlt. Why is that? Isn't it supposed to stall and only execute ISRs upon receiving interrupts?