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ah, well; the core and its drivers should be without any errors.
an automatic stack-switch (from ring3 to ring0) is only possible with TSS? and what to do in x84-64 in long mode, when there are no TSS anymore?

greets, hartyl

Yes, you are right. But, you can consider this one TSS, as a structure, which hold stacks. You don't have to use it for task switching.

There is an TSS in the x84-64 , and it must be used to hold rsp registers for each ring.
Anton.

It is needed to hold the stack registers, BTW there is no hardware task switching support under 32e mode.
Anton.

that was my point hardware task switching is not supported on either ia32e OR x86-64 but one is required to be loaded and it does more than just the stack
   "although the hardware task-switching mechanism is not supported in long mode, a 64-bit task state segment (TSS) MUST still exist. System software must create at least one 64-bit TSS for use after activating long mode, and it must execute the LTR instruction, in 64-bit mode, to load the TR register with a pointer to the 64-bit TSS that serves both 64-bit-mode programs and compatibility-mode programs."
besides the stack stuff the 64bit TSS also contains (and uses) the I/O permision map and mabey some other stuff not sure what else
(ref: AMD vol.#2 pg368-369)

there is also a new section in the 64-bit TSS that alows seperate stacks for specific ISRs (example: double fault, stack fault, or even page fault- any time you want to ensure a clean stack)
(REF: AMD vol.2 pg.290-291)

BTW: hartyl: do you have the hard-copy reference manuels? both are good though I prefer Intels especially that vol 2(instruction set reference) is only one book instead of three though either set will do fine for protected mode programming: excellent references and easier to use than the PDFs(though computer makes searching easier)