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I knew reads from 0x20 are persistant (opposite form 0x71) but i didnt know its documented, thx.
There is one more thing i forgot to mention about NMI:

0462 w Software NMI register. writing to this register causes an NMI
if NMI's are enabled
bit 7 = 1 generates an NMI

I want to generate NMI just for the sake of testing if port 0x70 mask really work.
I have my own isr of vector 2, i write to this port (byte, word, dword, 0x80, 0xFF, 0x8000, 0xFFFF, ...) and none of it work, my isr is never called.
I use bochs, this list is from bochs, so it should work.


Concerning PIC and eoi, i dont get one thing.
When i reporft EOI i use ocw2 (bit3 = 0, if 1 its ocw3). I use 'non specyfic EOI'.
However ocw2 has a field 'interrupt request to which the command applies' meaning i can select wich irq to reset.
PIC can send me only 1 interrupt at time, is it just for compatibility with cpus that can service many irqs at same time or what?


I more thinbg, does xt/at/ps2 describe overall machine architecture (like avaiability of certain devices, cpu type) or just cpu type
XT = 8088?
AT = ?
PS/2 = 8086?

XT, AT, and PS/2 referred to the computer as a whole, including processor, the motherboard devices like the PIT, the keyboard, etc.
XT and AT I think were mostly 8086/8088 machines. With PS/2 protected mode was introduced and I think they could have anything from an 8086 to an 80386.

For x86, the only kind of EOI you ever need to worry about and send is the non-specific EOI. All of the other ones were for other machines, or other uses which never found an application on x86 machines.

PC was 8088. XT was as well. AT was 80286. PS/2 will have had 80386 and later CPUs.

a5498828 wrote:datasheet doesnt say.

Liar

a5498828 wrote:I knew reads from 0x20 are persistant (opposite form 0x71) but i didnt know its documented, thx.

I hope that learnt you not to claim again something is undocumented, but instead blame your searching/reading skills.

All computer-related problems can be solved by either fixing the problem sitting behind the keyboard or buying new hardware - and we all know the latter doesn't apply here.

I have yet another problem with pic.
Many tutorials, including yours tell to map master on vector 8 (real mode).
But i have vectors 12 and 13 occupied by limit overflow. How can i map pic there if i have exceptions mapped to those vectors?
I map master at 0x20, and slave at 0x28. Is that ok? Why tutorials say to map on 0x8?

2 - In theory, is it possible that x86 could have 9 PIC chips (1 master, 8 slaves)?

a5498828 wrote:I have yet another problem with pic.
Many tutorials, including yours tell to map master on vector 8 (real mode).

Because that is the default mapping for Real Mode. The default mapping is at vector 0x8 for Master Controller and at vector 0x70 for Slave Controller.

But i have vectors 12 and 13 occupied by limit overflow. How can i map pic there if i have exceptions mapped to those vectors?

Map it to somewhere else.

I map master at 0x20, and slave at 0x28. Is that ok?

Yes it is, if you are in protected mode. This is just the general mapping to avoid Exceptions Vs IRQs identification conflict. You can map both the controller to different starting vectors as long as:
a. The starting vector is the mulitple of 8
b. The Mapping limit is not exceeded.

Why tutorials say to map on 0x8?

I'm not sure which tutorial says this. If it does, it might be talking about Real Mode and that is the default mapping for 'Master Controller'.

2 - In theory, is it possible that x86 could have 9 PIC chips (1 master, 8 slaves)?

Don't Know. Wait for other responses.

Hi,

a5498828 wrote:2 - In theory, is it possible that x86 could have 9 PIC chips (1 master, 8 slaves)?

The PIC chips were designed to support 0 to 8 slaves. You could probably even have 8 slaves and an 80x86 CPU; however, it wouldn't be "PC compatible" (it'd be some strange/different architecture that isn't compatible with anything).


Cheers,

Brendan