page enable problem

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pcmattman
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Re: page enable problem

Post by pcmattman »

Hi,

You've run into an incredibly familiar problem - I've struggled through this before. CR2 == CR0 at the time of the page fault.

Code: Select all

void page_enable(DWORD pdbr)
{
    __asm {
   mov   eax, pdbr
   mov   cr3, eax
   mov   eax, cr0
   or   eax, 0x80000000
   mov   cr0, eax
   }
}
I guess for starters you can implement that in assembly, so you have control over what the compiler emits. It shouldn't be too difficult, and it's good experience for you :)

EDIT: And by that, I mean implement the function itself in assembly, not just the body.
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kop99
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Re: page enable problem

Post by kop99 »

I'm really thank your reguards, pcmattman...

I've just changed my code....
following is the code...

in hal.asm file

Code: Select all

[bits 32]
global _page_enable

section .text

_page_enable:
	push	ebp
	mov	ebp, esp
	push	eax

	mov	eax, dword [ss:ebp + 8]
	mov	cr3, eax
	mov	eax, cr0
	or	eax, 0x80000000
	mov	cr0, eax

	pop	eax
	pop	ebp
	retn
but it still have the same problem....

and I think the problem is that cr3 register's content is still not page aligned...
here is current log : CR3=0x001043a0

any idea is helpful...
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pcmattman
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Re: page enable problem

Post by pcmattman »

Good catch of the CR3 issue. You mentioned previously this:
And I've also aleady aligned the swapper_pg_dir at 0x200000 and pg0 at 0x201000....
However, I can see that this isn't happening.

For the time being, you can do something like this:

Code: Select all

DWORD *swapper_pg_dir = (DWORD*) 0x200000;
DWORD *pg0 = (DWORD*) 0x201000;
However, this will not be very useful in the future - I highly suggest that, once you get this working, you start working on a page allocator. The wiki has a lot of information about them, so it should be rather straightforward. Then you won't need to hard-code values for your page directory and page tables, you can use your page allocator and obtain safe, page-aligned, addresses.
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kop99
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Re: page enable problem

Post by kop99 »

Well, Thank your reguards, combuster, NickJohnson and pcmattman....

I've just solved that problem...
i used lds script file's page aligned variables as page directory and page table 0....
so my simple kernel has no problem, now...

Thank you again... if there isn't your helps, i never solve that problem...
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Re: page enable problem

Post by pcmattman »

It's good to hear you've got it working, but I highly suggest you check out the wiki now before you continue. Specifically, the Page_Frame_Allocation article :)
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blackoil
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Re: page enable problem

Post by blackoil »

before enable paging,

set up basic PD, PT for identity mapping, it ensures all codes to be run at virtual address can operate correctly.
IDT entry should be virtual addr. maybe I am wrong, but I fill them with virtual addr.
adjust eip, esp, ebp register values to virtual addr.
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Brutus
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My own Paging problem

Post by Brutus »

Hello,

I am having some problems with paging. Could someone take a look?

Using GRUB (in case you need such info :)

Problem occurs when I set 1 bit of the CR0 to 1, then I get Triple Fault error.

Here are two parts of my code:
Physical memory manager

Code: Select all

#include <system.h>

extern unsigned int KERNEL_END;    // I get this from link.ld (linker)

unsigned int totalMemory;   // Memory size - couldn't make GRUB upper memory var work
unsigned int *pageableMemoryStart;
unsigned int pageableMemory;    // Memory, that is suitable for giving to processes
unsigned int unpageableMemory;  // Memory, that is not-suitable for that
unsigned int *MEMORY_MAP_START; 
int *MEMORY_MAP = (int *) &KERNEL_END;  /* MEMORY_MAP - array of int where MEMORY_MAP[0] shows first free frame and MEMORY[1] - shows first used frame (not the address, just array item, e.g. MEMORY[0] == 3, then address of that free frame is [KERNEL_END + 4MB (<- max array size for 4GB ram) + (3 - 2)*4096 ]) */

void pmm_install()
{
    unsigned int i;
    unsigned int x;

    unsigned int *ptr;
    unsigned int *ptrMem;   // Pointer'is realioje atmintyje
    int loopInt;            // Integer'is realios atminties surasymui i masyva

    unsigned int page2address;
    
    int tmp;
    int tmp2;
    
//*********************** END OF var *******************************************

//    print("Initializing physical memory management...\n");

    totalMemory = 0x6000000;    // 96MB

    MEMORY_MAP_START = MEMORY_MAP;

    pageableMemoryStart = MEMORY_MAP + 0x100000;   // 4MB for array
    ptrMem = pageableMemoryStart;

    x = (unsigned int)pageableMemoryStart;
    
    pageableMemory = (totalMemory - x) / 4096;   // pageable memory in pages
    unpageableMemory = ( x + 4096 ) / 4096;   // not pageable memory in pages


    MEMORY_MAP[0] = 2;          // free frames
    MEMORY_MAP[1] = -1;         // used frames - -1 means that there are no used pages
    
    for (loopInt = 2; loopInt < pageableMemory; loopInt++) // 1048576 - 4GB
    {
        if ((loopInt + 1) != pageableMemory)
        {
            MEMORY_MAP[loopInt] = loopInt + 1;
        } else { MEMORY_MAP[loopInt] = -1; }
    
    }
   
//    print("\nInitialization ended... Status: OK\n\n");
}

unsigned int pmmGetFrame() 
{
    unsigned int result;
    int x;
    int nextFreePage;
    int lastAssignedPage;
    
    if (MEMORY_MAP[0] != -1)
    {
        result = (unsigned int) pageableMemoryStart + ((MEMORY_MAP[0] - 2) * 4096);
        nextFreePage = MEMORY_MAP[0];
        MEMORY_MAP[0] = MEMORY_MAP[nextFreePage];
        lastAssignedPage = MEMORY_MAP[1];
        MEMORY_MAP[1] = nextFreePage;
        MEMORY_MAP[nextFreePage] = lastAssignedPage;
    } 
    else { result = 0; }
        
    return result;
}


void printMemoryMap(int max)
{
    int i;
    for (i = 0; i <= max; i++)
    {
        pr(MEMORY_MAP[i]);
        print(" ");
    }
    n();    // is like print("\n");
}


int pmmFreeFrame(unsigned int page) 
{
    int ret = 0;
    unsigned int freeFrame;
    unsigned int previous;
    unsigned int search;    
    
    freeFrame = page + 2;
    
    if (MEMORY_MAP[1] != freeFrame)
    {
        search = MEMORY_MAP[1];
        while ((MEMORY_MAP[search] != freeFrame) && (search != -1))
        {
            search = MEMORY_MAP[search];
        }

        if (search == -1)
        {
            return 1;
        }
        
        previous = search;
        MEMORY_MAP[previous] = MEMORY_MAP[freeFrame];
        MEMORY_MAP[freeFrame] = MEMORY_MAP[0];
        MEMORY_MAP[0] = freeFrame;
    } else {
        MEMORY_MAP[1] = MEMORY_MAP[freeFrame];
        MEMORY_MAP[freeFrame] = MEMORY_MAP[0];
        MEMORY_MAP[0] = freeFrame;
    }
    return ret;     // 1 - puslapis neuzimtas
}

Paging:

Code: Select all

#include <system.h>


void sendToCR3(unsigned int value)
{
    asm volatile("mov %0, %%cr3":: "r"(value));    // Nustatom PageDir CR3     
}

void sendToCR0 ()
{
   unsigned int cr0;
   asm volatile("mov %%cr0, %0": "=r"(cr0));    // Gaunam CR0 reiksme
   cr0 = cr0 | 0x80000000;
   asm volatile("mov %0, %%cr0":: "r"(cr0));    // Paleidziam pageing'a
}

void paging_install2()
{
    unsigned int *PDptr = (unsigned int *)pmmGetFrame();
    unsigned int *PTptr = (unsigned int *)pmmGetFrame();
    unsigned int *ptrInPD = PDptr;     // ptrInPD == Pointer in Page Directory
    unsigned int *ptrInPT = PTptr;     // ptrInPT == Pointer in Page Table
    unsigned int page20;                // 20 bit frame number will be stored here
    unsigned int page;                  // for loop
    unsigned int lastPage = totalMemory / 4096;
    unsigned int count1024 = 0;         // counter for creating new PT
    unsigned int addressFromPTE; 
    unsigned int value;
    
    page20 = (unsigned int)PTptr >> 12;

    *ptrInPD |= 0x80000000;                 // Setting that PT is Present in PD
    *ptrInPD |= page20;                     // Address (frame number) of PT in PD

    ptrInPD++;                      // + Move pointer in PD by 4 bytes


    
//    *ptrInPT |= 0x80000000;
    
    for (page = 0; page < lastPage; page++)     // Paging memory from 0x0000 0000 to [lastPage*4096]
    {
        if ((page % 1024 == 0) && (page != 0))    // This loop is for checking if the end of PT is not reached yet
        {
            PTptr = (unsigned int *)pmmGetFrame();
            page20 = (unsigned int)PTptr >> 12;
            *ptrInPD |= 0xA0000000;     // Nustatom Present-PT kataloge
            *ptrInPD |= page20;         // Nustatom Address (frame)-PT kataloge
            ptrInPD++;
            ptrInPT = PTptr;
        }

        page20 = (page * 4096) >> 12;
        *ptrInPT |= 0xA0000000;     // Present-page in PT
        *ptrInPT |= page20;         // Address (frame number) in PT

        ptrInPT++;
      
    }

    sendToCR3((unsigned int)PDptr);
//    sendToCR0();      // <<------ HERE I START PAGING
    
}
Any thoughts?

Thank you in advance.

Cheers,
Martin
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kop99
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Re: page enable problem

Post by kop99 »

Brutus,
Would you show me a Bochs log or something showing the state before the triple fault?
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Brutus
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Re: page enable problem

Post by Brutus »

kop99 wrote:Brutus,
Would you show me a Bochs log or something showing the state before the triple fault?
Qemu will be ok?
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kop99
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Re: page enable problem

Post by kop99 »

Qemu will be ok?
if Qemu's log have register status when triple fault ocurred, it's ok...

And I think the best emulator for os development is Bochs...
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Brutus
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Re: page enable problem

Post by Brutus »

kop99 wrote:
Qemu will be ok?
if Qemu's log have register status when triple fault ocurred, it's ok...

And I think the best emulator for os development is Bochs...
I had some problems setting Bochs up, but now I have somthing, thou it works a bit slowish somtimes.

Log:

Code: Select all

00000000000i[     ] Bochs x86 Emulator 2.4
00000000000i[     ]   Build from CVS snapshot on May 3, 2009
00000000000i[     ] System configuration
00000000000i[     ]   processors: 1 (cores=1, HT threads=1)
00000000000i[     ]   A20 line support: yes
00000000000i[     ] CPU configuration
00000000000i[     ]   level: 6
00000000000i[     ]   SMP support: no
00000000000i[     ]   APIC support: yes
00000000000i[     ]   FPU support: yes
00000000000i[     ]   MMX support: yes
00000000000i[     ]   SSE support: 2
00000000000i[     ]   CLFLUSH support: yes
00000000000i[     ]   VME support: yes
00000000000i[     ]   3dnow! support: no
00000000000i[     ]   PAE support: yes
00000000000i[     ]   PGE support: yes
00000000000i[     ]   PSE support: yes
00000000000i[     ]   1G paging support: no
00000000000i[     ]   x86-64 support: yes
00000000000i[     ]   SEP support: yes
00000000000i[     ]   MWAIT support: no
00000000000i[     ]   XSAVE support: no
00000000000i[     ]   AES support: no
00000000000i[     ]   VMX support: no
00000000000i[     ] Optimization configuration
00000000000i[     ]   RepeatSpeedups support: yes
00000000000i[     ]   Trace cache support: yes
00000000000i[     ]   Fast function calls: yes
00000000000i[     ] Devices configuration
00000000000i[     ]   ACPI support: yes
00000000000i[     ]   NE2000 support: yes
00000000000i[     ]   PCI support: yes
00000000000i[     ]   SB16 support: yes
00000000000i[     ]   USB support: yes
00000000000i[     ]   VGA extension support: vbe cirrus
00000000000i[MEM0 ] allocated memory at 02540020. after alignment, vector=02541000
00000000000i[MEM0 ] 96,00MB
00000000000i[MEM0 ] rom at 0xfffe0000/131072 ('C:\Program Files\Bochs\BIOS-bochs-latest')
00000000000i[MEM0 ] rom at 0xc0000/40448 ('C:\Program Files\Bochs\VGABIOS-lgpl-latest')
00000000000i[CMOS ] Using local time for initial clock
00000000000i[CMOS ] Setting initial clock to: Fri May 29 14:28:21 2009 (time0=1243596501)
00000000000i[DMA  ] channel 4 used by cascade
00000000000i[DMA  ] channel 2 used by Floppy Drive
00000000000i[FDD  ] fd0: 'Grub_.img' ro=0, h=2,t=80,spt=18
00000000000i[PCI  ] 440FX Host bridge present at device 0, function 0
00000000000i[PCI  ] PIIX3 PCI-to-ISA bridge present at device 1, function 0
00000000000i[MEM0 ] Register memory access handlers: 0x000a0000 - 0x000bffff
00000000000i[WGUI ] Desktop Window dimensions: 1024 x 768
00000000000i[WGUI ] Number of Mouse Buttons = 5
00000000000i[WGUI ] IME disabled
00000000000i[MEM0 ] Register memory access handlers: 0xe0000000 - 0xe0ffffff
00000000000i[CLVGA] VBE Bochs Display Extension Enabled
00000000000i[CLVGA] interval=50000
00000000000i[     ] init_dev of 'unmapped' plugin device by virtual method
00000000000i[     ] init_dev of 'biosdev' plugin device by virtual method
00000000000i[     ] init_dev of 'speaker' plugin device by virtual method
00000000000i[     ] init_dev of 'extfpuirq' plugin device by virtual method
00000000000i[     ] init_dev of 'gameport' plugin device by virtual method
00000000000i[     ] init_dev of 'pci_ide' plugin device by virtual method
00000000000i[PCI  ] PIIX3 PCI IDE controller present at device 1, function 1
00000000000i[     ] init_dev of 'acpi' plugin device by virtual method
00000000000i[PCI  ] ACPI Controller present at device 1, function 3
00000000000i[     ] init_dev of 'ioapic' plugin device by virtual method
00000000000i[IOAP ] initializing I/O APIC
00000000000i[MEM0 ] Register memory access handlers: 0xfec00000 - 0xfec00fff
00000000000i[     ] init_dev of 'keyboard' plugin device by virtual method
00000000000i[KBD  ] will paste characters every 1000 keyboard ticks
00000000000i[     ] init_dev of 'harddrv' plugin device by virtual method
00000000000i[HD   ] Using boot sequence floppy, none, none
00000000000i[HD   ] Floppy boot signature check is enabled
00000000000i[     ] init_dev of 'serial' plugin device by virtual method
00000000000i[SER  ] com1 at 0x03f8 irq 4
00000000000i[     ] init_dev of 'parallel' plugin device by virtual method
00000000000i[PAR  ] parallel port 1 at 0x0378 irq 7
00000000000i[     ] register state of 'unmapped' plugin device by virtual method
00000000000i[     ] register state of 'biosdev' plugin device by virtual method
00000000000i[     ] register state of 'speaker' plugin device by virtual method
00000000000i[     ] register state of 'extfpuirq' plugin device by virtual method
00000000000i[     ] register state of 'gameport' plugin device by virtual method
00000000000i[     ] register state of 'pci_ide' plugin device by virtual method
00000000000i[     ] register state of 'acpi' plugin device by virtual method
00000000000i[     ] register state of 'ioapic' plugin device by virtual method
00000000000i[     ] register state of 'keyboard' plugin device by virtual method
00000000000i[     ] register state of 'harddrv' plugin device by virtual method
00000000000i[     ] register state of 'serial' plugin device by virtual method
00000000000i[     ] register state of 'parallel' plugin device by virtual method
00000000000i[SYS  ] bx_pc_system_c::Reset(HARDWARE) called
00000000000i[CPU0 ] cpu hardware reset
00000000000i[APIC0] local apic 0 initializing
00000000000i[APIC0] allocate APIC id=0 (MMIO enabled) to 0xfee00000
00000000000i[     ] reset of 'unmapped' plugin device by virtual method
00000000000i[     ] reset of 'biosdev' plugin device by virtual method
00000000000i[     ] reset of 'speaker' plugin device by virtual method
00000000000i[     ] reset of 'extfpuirq' plugin device by virtual method
00000000000i[     ] reset of 'gameport' plugin device by virtual method
00000000000i[     ] reset of 'pci_ide' plugin device by virtual method
00000000000i[     ] reset of 'acpi' plugin device by virtual method
00000000000i[     ] reset of 'ioapic' plugin device by virtual method
00000000000i[     ] reset of 'keyboard' plugin device by virtual method
00000000000i[     ] reset of 'harddrv' plugin device by virtual method
00000000000i[     ] reset of 'serial' plugin device by virtual method
00000000000i[     ] reset of 'parallel' plugin device by virtual method
00000003305i[BIOS ] $Revision: 1.231 $ $Date: 2009/04/26 17:17:07 $
00000200000i[WGUI ] dimension update x=720 y=400 fontheight=16 fontwidth=9 bpp=8
00000318060i[KBD  ] reset-disable command received
00000444780i[VBIOS] VGABios $Id: vgabios.c,v 1.69 2009/04/07 18:18:20 vruppert Exp $

00000444851i[CLVGA] VBE known Display Interface b0c0
00000444883i[CLVGA] VBE known Display Interface b0c5
00000447808i[VBIOS] VBE Bios $Id: vbe.c,v 1.62 2009/01/25 15:46:25 vruppert Exp $
00000754369i[BIOS ] Starting rombios32
00000754866i[BIOS ] Shutdown flag 0
00000755547i[BIOS ] ram_size=0x06000000
00000756025i[BIOS ] ram_end=96MB
00000796633i[BIOS ] Found 1 cpu(s)
00000815668i[BIOS ] bios_table_addr: 0x000fb9a8 end=0x000fcc00
00000815776i[PCI  ] 440FX PMC write to PAM register 59 (TLB Flush)
00001143473i[PCI  ] 440FX PMC write to PAM register 59 (TLB Flush)
00001471401i[P2I  ] PCI IRQ routing: PIRQA# set to 0x0b
00001471422i[P2I  ] PCI IRQ routing: PIRQB# set to 0x09
00001471443i[P2I  ] PCI IRQ routing: PIRQC# set to 0x0b
00001471464i[P2I  ] PCI IRQ routing: PIRQD# set to 0x09
00001471474i[P2I  ] write: ELCR2 = 0x0a
00001472359i[BIOS ] PIIX3/PIIX4 init: elcr=00 0a
00001480317i[BIOS ] PCI: bus=0 devfn=0x00: vendor_id=0x8086 device_id=0x1237 class=0x0600
00001482893i[BIOS ] PCI: bus=0 devfn=0x08: vendor_id=0x8086 device_id=0x7000 class=0x0601
00001485308i[BIOS ] PCI: bus=0 devfn=0x09: vendor_id=0x8086 device_id=0x7010 class=0x0101
00001485548i[PIDE ] new BM-DMA address: 0xc000
00001486252i[BIOS ] region 4: 0x0000c000
00001488566i[BIOS ] PCI: bus=0 devfn=0x0b: vendor_id=0x8086 device_id=0x7113 class=0x0680
00001488818i[ACPI ] new irq line = 11
00001488832i[ACPI ] new irq line = 9
00001488862i[ACPI ] new PM base address: 0xb000
00001488876i[ACPI ] new SM base address: 0xb100
00001488904i[PCI  ] setting SMRAM control register to 0x4a
00001652998i[CPU0 ] Enter to System Management Mode
00001653008i[CPU0 ] RSM: Resuming from System Management Mode
00001817028i[PCI  ] setting SMRAM control register to 0x0a
00001826197i[BIOS ] MP table addr=0x000fba80 MPC table addr=0x000fb9b0 size=0xd0
00001828139i[BIOS ] SMBIOS table addr=0x000fba90
00001830523i[BIOS ] ACPI tables: RSDP addr=0x000fbba0 ACPI DATA addr=0x05ff0000 size=0x988
00001833762i[BIOS ] Firmware waking vector 0x5ff00cc
00001844875i[PCI  ] 440FX PMC write to PAM register 59 (TLB Flush)
00001845719i[BIOS ] bios_table_cur_addr: 0x000fbbc4
00014041523i[BIOS ] Booting from 0000:7c00
00044469905e[CPU0 ] interrupt(): gate descriptor is not valid sys seg (vector=0x0e)
00044469905e[CPU0 ] interrupt(): gate descriptor is not valid sys seg (vector=0x08)
00044469905i[CPU0 ] CPU is in protected mode (active)
00044469905i[CPU0 ] CS.d_b = 32 bit
00044469905i[CPU0 ] SS.d_b = 32 bit
00044469905i[CPU0 ] EFER   = 0x00000000
00044469905i[CPU0 ] | RAX=00000000e0000011  RBX=0000000000026260
00044469905i[CPU0 ] | RCX=0000000000520ffc  RDX=0000000000520ffc
00044469905i[CPU0 ] | RSP=0000000000106fb4  RBP=0000000000106fb8
00044469905i[CPU0 ] | RSI=00000000000263d3  RDI=00000000000263dc
00044469905i[CPU0 ] |  R8=0000000000000000   R9=0000000000000000
00044469905i[CPU0 ] | R10=0000000000000000  R11=0000000000000000
00044469905i[CPU0 ] | R12=0000000000000000  R13=0000000000000000
00044469905i[CPU0 ] | R14=0000000000000000  R15=0000000000000000
00044469905i[CPU0 ] | IOPL=0 id vip vif ac vm RF nt of df if tf SF zf af PF cf
00044469905i[CPU0 ] | SEG selector     base    limit G D
00044469905i[CPU0 ] | SEG sltr(index|ti|rpl)     base    limit G D
00044469905i[CPU0 ] |  CS:0008( 0001| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  DS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  SS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  ES:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  FS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  GS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  MSR_FS_BASE:0000000000000000
00044469905i[CPU0 ] |  MSR_GS_BASE:0000000000000000
00044469905i[CPU0 ] | RIP=00000000001030f7 (00000000001030f7)
00044469905i[CPU0 ] | CR0=0xe0000011 CR2=0x00000000e0000011
00044469905i[CPU0 ] | CR3=0x00508000 CR4=0x00000000
00044469905i[CPU0 ] 0x00000000001030f7>> add byte ptr ds:[eax], al : 0000
00044469905p[CPU0 ] >>PANIC<< exception(): 3rd (13) exception with no resolution
00044469905i[CPU0 ] CPU is in protected mode (active)
00044469905i[CPU0 ] CS.d_b = 32 bit
00044469905i[CPU0 ] SS.d_b = 32 bit
00044469905i[CPU0 ] EFER   = 0x00000000
00044469905i[CPU0 ] | RAX=00000000e0000011  RBX=0000000000026260
00044469905i[CPU0 ] | RCX=0000000000520ffc  RDX=0000000000520ffc
00044469905i[CPU0 ] | RSP=0000000000106fb4  RBP=0000000000106fb8
00044469905i[CPU0 ] | RSI=00000000000263d3  RDI=00000000000263dc
00044469905i[CPU0 ] |  R8=0000000000000000   R9=0000000000000000
00044469905i[CPU0 ] | R10=0000000000000000  R11=0000000000000000
00044469905i[CPU0 ] | R12=0000000000000000  R13=0000000000000000
00044469905i[CPU0 ] | R14=0000000000000000  R15=0000000000000000
00044469905i[CPU0 ] | IOPL=0 id vip vif ac vm RF nt of df if tf SF zf af PF cf
00044469905i[CPU0 ] | SEG selector     base    limit G D
00044469905i[CPU0 ] | SEG sltr(index|ti|rpl)     base    limit G D
00044469905i[CPU0 ] |  CS:0008( 0001| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  DS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  SS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  ES:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  FS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  GS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00044469905i[CPU0 ] |  MSR_FS_BASE:0000000000000000
00044469905i[CPU0 ] |  MSR_GS_BASE:0000000000000000
00044469905i[CPU0 ] | RIP=00000000001030f7 (00000000001030f7)
00044469905i[CPU0 ] | CR0=0xe0000011 CR2=0x00000000e0000011
00044469905i[CPU0 ] | CR3=0x00508000 CR4=0x00000000
00044469905i[CPU0 ] 0x00000000001030f7>> add byte ptr ds:[eax], al : 0000
00044469905i[CMOS ] Last time is 1243596512 (Fri May 29 14:28:32 2009)
00044469905i[     ] restoring default signal behavior
00044469905i[CTRL ] quit_sim called with exit code 1
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Brutus
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Re: page enable problem

Post by Brutus »

Anyone any idea? :/
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Combuster
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Re: page enable problem

Post by Combuster »

Your paging structures are broken - your kernel code disappears after you enabled paging. (CR2 = CR0)
"Certainly avoid yourself. He is a newbie and might not realize it. You'll hate his code deeply a few years down the road." - Sortie
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Brutus
Posts: 8
Joined: Fri May 29, 2009 1:04 am

Re: page enable problem

Post by Brutus »

Combuster wrote:Your paging structures are broken - your kernel code disappears after you enabled paging. (CR2 = CR0)
But I don't get it, why is it wrong :cry:

I've just tried to change mapping from all memory, to just 1 PT (0...1023 frames) to see if the problem is there, same thing. I also tried setting Present + Supervisor and Read/Write - didn't help. I'm trying to work this thing out for two weeks now :(
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pcmattman
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Re: page enable problem

Post by pcmattman »

Hi,

Code: Select all

CR2=0x00000000e0000011
CR2 == CR0. Combuster pointed it out already, but that specific value is what is supposed to be written to CR0 and not addressed.

I've noticed this happens quite regularly, and whilst I'm not sure as to how to solve it, I personally think the easiest solution is to implement your reads/writes to CR0 in pure assembly. A bit like this (AT&T syntax):

Code: Select all

.global readCR0 # uint32_t readCR0()
.global writeCR0 # void writeCR0(uint32_t cr0)

readCR0:
    mov %cr0, %eax
    ret

writeCR0:
    push ebp
    mov ebp, esp

    mov 8(%ebp), %eax
    mov %eax, %cr0

    mov esp, ebp
    pop ebp
    ret
Another potential idea is to use a specific register, say "a", for the sendToCR0() calls (which, according to the intel manuals, should not be required). Let me know if either of these work.
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