To summarize the situation:
- Intel processors (and clones) only allow to jump to code segments of the same level
- The "call gates" can give you access to a more priviledged segment, but never to a less priviledged one.
- When the CPU uses a call gate (or an interrupt gate) and has to do a level switch, it pushes additionnal info on the stack. It detect those infos should be restored by comparing the CPL to the RPL of the code selector to return to.
IIrc, that "extra information" consist of stack segment & pointer and content of all the data selectors.
AT&T syntax
- Pype.Clicker
- Member
- Posts: 5964
- Joined: Wed Oct 18, 2006 2:31 am
- Location: In a galaxy, far, far away
- Contact:
Re:AT&T syntax
Hi,
Pype is right - for a privelege level change, IRET pops EIP, CS, EFLAGS, then ESP and SS (but none of the data segment registers - that's for virtual 8086 mode only AFAIK).
Cheers,
Brendan
Duh! Sorry - didn't notice it there..DruG5t0r3 wrote:"pushfl"
Doesn't that push the EFLAGS?
Pype is right - for a privelege level change, IRET pops EIP, CS, EFLAGS, then ESP and SS (but none of the data segment registers - that's for virtual 8086 mode only AFAIK).
Cheers,
Brendan
For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.
Re:AT&T syntax
It's WorrrkKKiiiNg. =)
But it looks like it was more than just loading the proper SS and ESP. You had to load DS,ES and etc to a ring 3 selector too.
But it looks like it was more than just loading the proper SS and ESP. You had to load DS,ES and etc to a ring 3 selector too.
Re:AT&T syntax
Hi,
Cheers,
Brendan
You must have DS and ES set to somethijg CPL=3 code can use before it uses them, but the IRET will not load them from the stack like it does SS:ESP....DruG5t0r3 wrote:But it looks like it was more than just loading the proper SS and ESP. You had to load DS,ES and etc to a ring 3 selector too.
Cheers,
Brendan
For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.
Re:AT&T syntax
Now my second problem emerges. Whenever I try to access memory or write to memory from my ring 3 code I get a page fault.
I'm fairly sure this is due to Page permission problem being in supervisor mode or something. The only thing is, I've set ALL of my pages to user mode just in case and it still doesn't work. Any other suggestions?
I'm fairly sure this is due to Page permission problem being in supervisor mode or something. The only thing is, I've set ALL of my pages to user mode just in case and it still doesn't work. Any other suggestions?
- Pype.Clicker
- Member
- Posts: 5964
- Joined: Wed Oct 18, 2006 2:31 am
- Location: In a galaxy, far, far away
- Contact:
Re:AT&T syntax
just make sure that
- pages of your code are user-enabled
- pages for your data are user-enabled
- pages for your stack are user-enabled
- directories that contain any user-enabled page are user-enabled aswell.
- pages of your code are user-enabled
- pages for your data are user-enabled
- pages for your stack are user-enabled
- directories that contain any user-enabled page are user-enabled aswell.
Re:AT&T syntax
OK, it works, but it wasn't because I haven't set all the pages to user mode, but because I haven't set the "write" bit in the appropriate pages.
Thanks guys...Looks like I can make this work after all
Thanks guys...Looks like I can make this work after all