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GDT calculations are based on physical references and is also done before any paging and (of course) any segmentation is done.

No. Look at section 2.4.1 and 2.4.3 in the Intel manuals: both GDTR and IDTR contains linear address, not physical address. That clearly means (according to figure 3-1) that this address still has to go through paging system before resolved.

(don't take it hardly: i did the same mistake one year ago)

What the...looks like you're right for the GDTR, it holds a _linear_ address.
But what about the base address in a segment descriptor? I'm fairly sure it holds a physical addres.

A GDT permission can override a page permission, but not the contrary.

What do you mean with "a GDT permission" ? and how should i interprete "override" ? ... If a segment descriptor tells i can write to a segment but the page isn't writable, i cannot write. And similarily, if a segment tells i cannot write, i cannot write regardless of what the page can do. So you actually AND permissions together to know what you can do.

Lets say for instance that you have segment descriptor for a data segment that is read-only, if it refers to a read/write page, it will be read-only, not read/write.

Same things apply for IDT.

Indeed, IDT works as GDT (that is, affected by paging)

[quote

And as for PDT...as long as they are physically 4096 byte alligned, they can be non-continuous.

no reference to "PDT" found in the intel manual. What are you talking about, exactly ? page tables ?

Page Directory Tables and Page tables.

[quote author=DruG5t0r3
What the...looks like you're right for the GDTR, it holds a _linear_ address.
But what about the base address in a segment descriptor? I'm fairly sure it holds a physical addres.

Then, you're fairly wrong. Any thing that is the 'base' of a segment (including base of a TSS, base of a data/code segment, base of a LDT, base of a GDT, or base of the IDT) in intel architecture (at least from 386) is a linear address.

The exact oddities with TSS and paging is

If paging is used, care should be taken to avoid placing a page boundary within the part of the TSS that the processor reads during a task switch (the first 104 bytes). If a page boundary is placed within this part of the TSS, the pages on either side of the boundary must be present at the same time and contiguous in physical memory.

Which simply means that one should not rely on paging while in the middle of a hardware switch. If your TSS has an IObitmap, however, that one could come on whatever page you'll like.

Lets say for instance that you have segment descriptor for a data segment that is read-only, if it refers to a read/write page, it will be read-only, not read/write.

True (that's basically what i said) and the opposite applies aswell, so imvho there's not one mechanism that superseeds the other one: they both apply.

Funny that we refer to that book as if it was a bible...

"Please refer to Section 2.3.4 in your Bible"..

Hi,

Pype.Clicker wrote: in the case of "demand paging", one can rather easily add page colouring by creating N "page pools" (one per colour) and change the virtual memory management so that page for virtual colour i is requested from pool of colour i.

For free page stacks, yes. For the bitmap approach it's also relatively easy to find a page of the right colour while still using a single bitmap.

Pype.Clicker wrote:Things become harder to do if you want to ask several physical pages in a row.

Not really. If the first physical page is of the right colour, then any contiguous physical pages will also be of the right colours.

There are only 2 real difficulties. The first is auto-detecting the number of page colours you should be using (AFAIK FreeBSD and NetBSD don't bother - it needs to be set manually or left at the default). On newer CPUs enough information can be obtained via. CPUID, but Intel and AMD use different methods.

The second difficulty is handling the case where there are no free pages of the correct colour. In this case you could simply give up and use any physical page, or you could try for the "next best" page colour. For example, if you're using 128 page colours and need page colour N, then the second best page colour can be found by N XOR (128/2). This only works when the number of page colours is a power of 2 (but it should be a power of 2 anyway). Similarly the third and fourth best page colours can be found by N XOR (128/4) and N XOR (128/2) XOR (128/4). This is all a bit extreme though - if you've run out of pages of the right page colour then finding a good alternative is the least of your problems.

Supporting page colouring does complicate the physical memory manager a bit though (especially if the physical memory manager deals with other options like NUMA and PAE at the same time).


Cheers,

Brendan

actualy after enabling paging only the page directory table pointed by CR3 register must be a phyisical address. other linear address whatever it is goes throw paging.