Looks like Intel's Core Duo Errata list is growing....

[Brynet-Inc]

I was reading the OpenBSD misc mailing lists and noticed an announcement by Theo about a lot of "bugs/defects" in Intel's Core Duo processors.

Quite an interesting read.. That's for sure.
http://marc.info/?t=118296457100003&r=1&w=2 (Read from the bottom up..)

Summary:
http://www.geek.com/images/geeknews/200 ... __full.gif
Current Errata:
http://download.intel.com/design/proces ... 327914.pdf

[Combuster]

from the same mailing list:

> > (While here, I would like to say that AMD is becoming less helpful day
> > by day towards open source operating systems too, perhaps because
> > their serious errata lists are growing rapidly too).

So, what remains?

[Brendan]

Hi,

I was reading the OpenBSD misc mailing lists and noticed an announcement by Theo about a lot of "bugs/defects" in Intel's Core Duo processors.

Every time Intel release a new processor they get a new list of errata, and some morons look at the (very brief) bug descriptions and poo their pants, without reading the entire description or considering how the bug could effect any real OS.


AE4/AI59 - Code limit violation may occur on 4 GB limit check

Reported by morons as "Showstopper - could be exploited by a virus - though unlikely"

Full description by Intel: Code Segment limit violation may occur on 4 Gigabyte limit check when the code stream wraps around in a way that one instruction ends at the last byte of the segment and the next instruction begins at 0x0.

My thoughts: Won't effect any 64-bit code as there is no 4 GB code segment limit or wrap-around. Won't effect any 32-bit OS that uses the first page of each linear address space to catch NULL pointer bugs. Won't effect any 32-bit OS that doesn't allow code in the highest page of the linear address space.

For my OS: The first page in linear address space is used to catch NULL pointers and the last page contains paging structure data that is CPL=0 only data. Total impact on me (and most OSs) - completely ignorable in all cases.


AE4/AI59 - REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations

Reported by morons as "Showstopper, but only observed by Intel so far"

Full description by Intel: Under certain conditions as described in the Software Developers Manual section “Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processorsâ€