With the I/O and Local APICs, what state are they in when you start execution of your code?
Do they need to be programmed to send interrupts to the boot processor, merely enabled, or something much more elaborate? All documentation on the web, including Intel's seems lacking in saying what NEEDS to be done instead of what can be done. If I merely need to enable them, and load the IDT, that would be terrific at this point.
At this point, I simply want to add an IDT, and a keyboard handler, and merely test its working. Currently the system has not touched interrupts at all, no idt loaded, no sti executed, etc.
Thanks in advance
APIC question, maybe for Xenos?
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Xenos
RE:APIC question, maybe for Xenos?
Normally the Local APICs are disabled and I/O APICs are either in Virtual Wire or PIC mode, meaning the whole system is looking like an IBM PC with a 8086 processor. That also means that it looks like a single processor system.
How to add a keyboard handler depends on which way it should work: With inly one CPU running, always interrupting the same CPU with sevral CPUs running or interrupt the CPU with the lowest priority task running?
The first is the simplest: It works like on a single processor system. Set up an IDT with an appropriate keyboard handler entry and enable interrupts.
The second could be done in Virtual Wire mode. There's a BIOS code example on how to set up Virtual Wire mode in Intel's multiprocessor specification.
The third is the most interesting way. You need to activate secondary CPUs, activate their Local APICs and set the interrupt delivery mode of the keyboard interrupt to "lowest priority" using the I/O APIC. (There's a datasheet for the I/O APIC which I can't find at the moment - you need to set the interrupt mode registers.) Then you can assign an interrupt vector and place the keyboard handler at that vector in the IDT.
How to add a keyboard handler depends on which way it should work: With inly one CPU running, always interrupting the same CPU with sevral CPUs running or interrupt the CPU with the lowest priority task running?
The first is the simplest: It works like on a single processor system. Set up an IDT with an appropriate keyboard handler entry and enable interrupts.
The second could be done in Virtual Wire mode. There's a BIOS code example on how to set up Virtual Wire mode in Intel's multiprocessor specification.
The third is the most interesting way. You need to activate secondary CPUs, activate their Local APICs and set the interrupt delivery mode of the keyboard interrupt to "lowest priority" using the I/O APIC. (There's a datasheet for the I/O APIC which I can't find at the moment - you need to set the interrupt mode registers.) Then you can assign an interrupt vector and place the keyboard handler at that vector in the IDT.