Hello Everyone...
This is my first post...
I m working on os project from few weeks..
my scheduler on single processor is working fine...
but dont know how to implement per processor data...
for e.q. to store thread que for each processor...
how do sheduler know from which processor it is running and how to access data for dat processor...
please help me..
Per Processor Data
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sid.koolwizard
- Posts: 3
- Joined: Sun Feb 25, 2007 4:56 am
There is the Multiprocessor Specification, which will tell you how to startup the other processors. You can identify the processors by their APIC Id, which is unique for every cpu. But remember that you need some spinlocks/mutex/semaphore code...
Re: Per Processor Data
Hi,
For this you'd need a 256 entry array (but with paging and large "CPU data structures" you don't need to map RAM to entries for CPUs that aren't present).
I also setup FS base differently on each CPU so that ir points to the CPU's entry in the array. This means that most of the time (unless you're looking at one CPUs data from another CPU) you can just use a segment override instead of finding the address of the entry in the array.
For TSSs, it's easy enough to put each CPUs TSS data into it's "CPU data structure", along with scheduler queues, CPU identification, locality information, etc.
Cheers,
Brendan
I use an array of "CPU data structures" where the CPUs local APIC ID is an index into this array. Local APIC ID's are 8-bit, fast to find and guaranteed to be unique.sid.koolwizard wrote:I m working on os project from few weeks..
my scheduler on single processor is working fine...
but dont know how to implement per processor data...
for e.q. to store thread que for each processor...
how do sheduler know from which processor it is running and how to access data for dat processor...
For this you'd need a 256 entry array (but with paging and large "CPU data structures" you don't need to map RAM to entries for CPUs that aren't present).
I also setup FS base differently on each CPU so that ir points to the CPU's entry in the array. This means that most of the time (unless you're looking at one CPUs data from another CPU) you can just use a segment override instead of finding the address of the entry in the array.
For TSSs, it's easy enough to put each CPUs TSS data into it's "CPU data structure", along with scheduler queues, CPU identification, locality information, etc.
Cheers,
Brendan
For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.
You need at least one TSS per processor, no matter what you do, because you need to have different ESP0 values in the TSS for each processor, so that if different processors get interrupts/exceptions from userspace at the same time, they don't try to use the same stack at the same time.sid.koolwizard wrote:I am using TSS but only single TSS for all the process...
but how know from which processor code is executing by TSS..
i mean in multi processor systems...
i want to implement SMP
Since interrupts/exceptions will push flags, cs, eip, and possibly errorcode (depending on exception) before you have chance to figure out what processor you are on, there's nothing you can do but have then use different stacks, mandating the use of separate TSSes for each processor.
Ofcourse one straight-forward implementation is to keep the kernel-stack of currently executing thread in relevant processors ESP0, then switching threads by swapping kernel-stacks, but whether or not you use this scheme, you can't avoid having separate TSS for each processor.
The real problem with goto is not with the control transfer, but with environments. Properly tail-recursive closures get both right.