IRQ6 and the FDC DOR

ManOfSteel · Post by **ManOfSteel** » Fri Dec 01, 2006 2:57 am

Hello,
I just have a little question: does sending a motor start command (with DMA on) to the DOR enables the sixth IRQ line on the 8259 PIC, too? I've already read the official manuals but I'm not 100% sure that's what they mean.
Thanks for your replies.

pulsar · Post by **pulsar** » Fri Dec 01, 2006 10:39 pm

There is no way starting the motor could send an interrupt. May be the steps you are performing before starting a motor could send an interrupt. If you want to test it put a delay routine for 10 seconds and see whether interrupt is still firing.

ManOfSteel · Post by **ManOfSteel** » Sat Dec 02, 2006 1:13 am

Hello,
I'm not talking about an interrupt firing. I'm talking about the 8259 PIC floppy line (6) being automatically enabled without being manually enabled by me.

Ok, that's what happened. I was recently programming a routine to enable/disable IRQ lines. I accidentally forgot to enable IRQ6. All IRQ lines (other than cascading) are initially disabled. I tested the OS and everthing was going fine. Later I realized that the IRQ line was never manually enabled (with my new routine).
I already have an entire driver for the FDC/DMA and on the real hardware as well as in an emulator it works normally even if I still haven't enabled the IRQ line on the 8259's port 21h.

In Intel's 82077AA document I read:

The DOR is also used to perform a software reset of the disk controller and tristate the DRQ2 and IRQ6 output signals on the PC bus.

So, what I'm asking is if this sentence above means that using the DOR to enable DMA transfers also enables the sixth IRQ line automatically without doing it manually by clearing the sixth bit of 8259's port 21h.
That's it.

ManOfSteel · Post by **ManOfSteel** » Mon Dec 04, 2006 5:48 am

So... Anyone? Anything?

Combuster · Post by **Combuster** » Mon Dec 04, 2006 9:28 am

Well, the reason for not posting is that those statements seem contradictory, but since you asked: you or someone else probably made a mistake somewhere. The problem is, I can only guess where it could have been.

AFAIK anything to do with the FDC doesnt change the interrupt mask at the PIC, and thus doesnt change wether irq 6 is being serviced or not. Tristating an output makes it officially indeterminate. What i do not know is wether its interpreted by the PIC as a 0 or a 1. In any case the signal can only drop to 0 which wouldnt raise an interrupt as it normally only does that on an rising edge.

That however doesnt explain why irq6 fires when disabled - personally i'd look for a bug in the PIC system - tried enabling and disabling IRQ 0 (PIT) or 1 (KBC) to see if the code works?

Brendan · Post by **Brendan** » Mon Dec 04, 2006 9:39 am

Hi,

ManOfSteel wrote:In Intel's 82077AA document I read:
The DOR is also used to perform a software reset of the disk controller and tristate the DRQ2 and IRQ6 output signals on the PC bus.
So, what I'm asking is if this sentence above means that using the DOR to enable DMA transfers also enables the sixth IRQ line automatically without doing it manually by clearing the sixth bit of 8259's port 21h.

It doesn't.

The bit in the DOR allows the IRQ to be sent from the floppy drive controller to the PIC chip, but has no control over what the PIC chip does if/when it receives an IRQ from the floppy drive controller.

I would assume Intel's datasheet refers to the original ISA bus (which has IRQ and DMA request lines that go from the PIC and DMA chips to all devices on the bus), although I don't know why it specifically says "the sixth IRQ line" - that is an implementation detail of the type that is rarely included in datasheets, because it won't be correct in some cases (e.g. a secondary floppy disk controller).

Cheers,

Brendan

smiddy · Post by **smiddy** » Mon Dec 04, 2006 9:44 am

I don't beleive that is what that is saying. It is merely pointing out that IQR6 will be OR-ed with DQR and DOR. It doesn't setup the PIC to receive the IRQ6 and process it, from what I gather from reading your post and the spec. I am assuming you've already setup DMA to receive the block of data, which is what I assume is happening? You can test if IRQ6 is actually firing...but it shouldn't be setup on the PIC unless you set it up. Also, if you didn't disable ALL the IQRs in your PIC prior (and initiallize them one at a time), the defaults will be already setup upon bootup process. Assuming you're using an IDT, you should have already assigned an INT for IRQ6 to handle it, disable it to an unhandled INT and let it fire away to test, I suspect, to check.

Of course, I may be wrong since I'm not certain what you're asking.