8259A Help need.

[Mikae]

Hello, all.

I read Intel's 8259A datasheet (uff, it is not too easy!), and almost understood its logic. But I can't understand, why SP/EN is needed? And when CAS lines are used?

Thanking in advance.

[Brynet-Inc]

Hello, all.

I read Intel's 8259A datashit (uff, it is not too easy!), and almost understood its logic. But I can't understand, why SP/EN is needed? And when CAS lines are used?

Thanking in advance.

Intel wrote a datashit eh?

I wonder what a datashit is...

[Mikae]

SH*T! Sheet... I missed )).

[Combuster]

I kindof wonder why you want to know how the PIC's electrics work, as thats something for hardware development.

From what i quickly read, the cascade lines are used when the second pic wants to interrupt the system: the slave pic raises the int line (connected to the master)
the master interrupts the cpu, and when the cpu acknowledges the interrupt the master uses the cascade lines to signal the slave that it should drive the data bus.

Actually, there's a sample schematic of a cascaded PIC on page 19 of the data sheet. If you ignore the second slave, thats pretty much how things are set up in a PC. (I'm not sure if the interrupt numbers match though)

[Mikae]

I kindof wonder why you want to know how the PIC's electrics work, as thats something for hardware development.

I am trying to know base system's component's interface too, not only from the point of view of software.

the master interrupts the cpu, and when the cpu acknowledges the interrupt the master uses the cascade lines to signal the slave that it should drive the data bus.

Hmm... Iam not sure. Every 8259 is connected to control bus, and has its own INTA...

[kataklinger]

I am trying to know base system's component's interface too, not only from the point of view of software.

If that's the reason why don't you study I/O APIC instead? I think it's more interesanting and if nothing else it's newer

[Mikae]

If that's the reason why don't you study I/O APIC instead?

As I understand, 8259 are used in every Intel's system chipset. Isn't it? Also, it was always a miracle for me, how interrupts are delivered to CPU. I knew something, but now I want to know in details.

[kataklinger]

As I understand, 8259 are used in every Intel's system chipset. Isn't it? Also, it was always a miracle for me, how interrupts are delivered to CPU. I knew something, but now I want to know in details.

Yes there is 8259 in every PC but it is an ancient interrupt controller, but APIC is much newer, and AFAIK it is present on every modern motherboard.

[Brendan]

Hi,

the master interrupts the cpu, and when the cpu acknowledges the interrupt the master uses the cascade lines to signal the slave that it should drive the data bus.

Hmm... Iam not sure. Every 8259 is connected to control bus, and has its own INTA...

To me, it looks like it goes like this:

• - slave PIC receives a signal on IR0 to IR7 pins
  - slave PIC raises it's INT line to tell the master it wants to send an IRQ
  - master PIC raises it's INT line to tell the host system it wants to send an IRQ
  - the host system raises the INTA line to tell all of the PICs it's ready to receive the IRQ
  - the master PIC sends a one byte code to the host to tell it the details on the way
  - the master PIC uses the CAS0 to CAS2 lines to tell the slave PIC to talk on the bus
  - the slave PIC sends the interrupt vector to the host system
  - the master PIC drops CAS0 to CAS2

Of course in a modern computer there are no 8259A chips - most (all?) of the ISA stuff is packed into a single larger chip, and the communication between the PICs is probably done differently. For e.g. imagine a wider PIC chip with IR0 to IR16 and some trickery to make it behave the same as a pair of 8259A chips, that supports non-buffered 8086 mode only.


Cheers,

Brendan

[Brendan]

Hi,

As I understand, 8259 are used in every Intel's system chipset. Isn't it? Also, it was always a miracle for me, how interrupts are delivered to CPU. I knew something, but now I want to know in details.

Yes there is 8259 in every PC but it is an ancient interrupt controller, but APIC is much newer, and AFAIK it is present on every modern motherboard.

One (or more) I/O APICs are present on all SMP motherboards since the 80486 (including "single socket" motherboards that support hyper-threading and/or multi-core chips). For motherboards made in the last 5 years it's likely there's an APIC regardless of whether "multi-CPU" is possible or not. IIRC Microsoft "asked" motherboard manufacturers to include it around that time (and it made sense due to Intel's plans).

For something like a single CPU Pentium III system it's likely there is no I/O APIC, and the I/O APIC can be more work to setup. IMHO unless you're writing a "64-bit only" OS it'd be worthwile learning about the PIC (and then learning about I/O APICs after that).


Cheers,

Brendan

[Mikae]

- the master PIC sends a one byte code to the host to tell it the details on the way

What do you mean? As I undesrtand, 8259 keeps silence after the first INTA and sends interrupt vector to data bus after the second INTA.

[Brendan]

Hi,

- the master PIC sends a one byte code to the host to tell it the details on the way

What do you mean? As I undesrtand, 8259 keeps silence after the first INTA and sends interrupt vector to data bus after the second INTA.

Doh! I was reading information for the protocol used for MCS-80, instead of the protocol that is used by 8086.

BTW to get a better pespective, it might be a fun to see how "8259A compatability" is implemented in a modern chipset - for an example, take a look at the datasheet for Intel's 865 chipset I/O controller hub.


Cheers,

Brendan

[Mikae]

Well, I think I understood, when CAS lines are needed. I didn't pay attetion for this paragraphs:

a. In the master mode (either when SP = 1, or in
buffered mode when M/S = 1 in ICW4) a ''1'' is
set for each slave in the system. The master then
will release byte 1 of the call sequence (for MCS-
80/85 system) and will enable the corresponding
slave to release bytes 2 and 3 (for 8086 only byte
2) through the cascade lines.

b. In the slave mode (either when SP = 0, or if BUF
= 1 and M/S = 0 in ICW4) bits 2-0 identify the
slave. The slave compares its cascade input with
these bits and, if they are equal, bytes 2 and 3 of
the call sequence (or just byte 2 for 8086) are
released by it on the Data Bus.

cause I didn't understand, why SP/EN is needed. Now I think, that SP means, that a number of slaves are presented.

[Mikae]

Well, I almost read my datashi... datasheet , and have one more question again.

How I can to determine, which mode, 'low-to-high transition' or just 'high level' uses my hardware to bring interrupt request to IR0-7? This is connected to ICW1, LTIM value.

[Brendan]

Hi,

How I can to determine, which mode, 'low-to-high transition' or just 'high level' uses my hardware to bring interrupt request to IR0-7? This is connected to ICW1, LTIM value.

For 80x86, the interrupt lines connected to the PIC are "edge triggered" (or "low-to-high transitions" are used to signal an IRQ to the PIC).

Of course nothing is quite that simple. For "many" EISA systems and (all?) PCI systems it's possible to set individual interrupt lines as either edge triggered or level triggered using I/O port 0x4D0 (for the master PIC's interrupts) and I/O port 0x4D0 (for the slave PIC's interrupts). I'm not too sure if this was originally done using an extra/external chip in conjunction with an 8259, or if true 8259 chips had stopped being used.

In general, all ISA/legacy devices generate edge triggered interrupts (which makes interrupt sharing impossible), and all PCI devices general level triggered interrupts (which makes interrupt sharing possible). I'm not sure about other bus types...


Cheers,

Brendan