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I've problems with leaving virtual 86 task. If I try to execute code with 'int' instruction (class3 interrupt) or code with infinite loop that allows me to press key (class1 interrupt - hardware) I'm getting in bochs
exception(): 3rd (14) exception with no resolution, shutdown status is 00h, resetting
(VME = 0 and DPL = 3 or less -> no difference) CR2 is pointing to 8th entry in IDT (double fault exception). All entrys in IDT are Task Gates because v86 tasks have PDT that covers only first MB.
When I'm getting those exceptions I'm still in v86 mode. It looks like after interrupt/exception processor is trying to get info from IDT about interrupt/exception handler but because IDT is not available due to lack of entry in PDT (at this moment I'm still using v86 PDT) I'm getting error. Is it good way of thinking or is there something else?
afaik, if a IRQ is received while in VM mode, then the CPU should switch to PMODE and run the appropriate irq handler as described by the IDT.
however, how a "INT nn" is handled may depend on misc. parameters (such as IOPL, VME bit, etc. which i have almost forgot about), but "default" behaviour is to issue a GPF.
Can your system handle a GPF properly ? My guess would be that it doesn't and the GPF transform in a double, then tripple fault.
Pype.Clicker wrote:
Well , problem is that it's not switching
however, how a "INT nn" is handled may depend on misc. parameters (such as IOPL, VME bit, etc. which i have almost forgot about), but "default" behaviour is to issue a GPF.
VME = 0, IOPL = 3 -> then 'int x' gives 'int x' in PM
VME = 0, IOPL < 3 -> then 'int x' always gives 'int 13' in PM
Pype.Clicker wrote:
Can your system handle a GPF properly ? My guess would be that it doesn't and the GPF transform in a double, then tripple fault.
You have of course given a proper ESP0 and SS0 value in the V86 TSS, right ? without that, it won't be able to handle your exception (or interrupt) properly.
Pype.Clicker wrote:
You have of course given a proper ESP0 and SS0 value in the V86 TSS, right ? without that, it won't be able to handle your exception (or interrupt) properly.
crackers wrote:
It looks like after interrupt/exception processor is trying to get info from IDT about interrupt/exception handler but because IDT is not available due to lack of entry in PDT (at this moment I'm still using v86 PDT) I'm getting error. Is it good way of thinking or is there something else?
Seems i have overlooked that. The IDT isn't mapped from your v86 task ? how do you expect any exception/interrupt to be processed then ?
Even if you install a task gate for a given interrupt, the processor still needs to be able to read the IDT to access it. What about mapping the IDT, but above 1MB so that it is out of virtual mode's reach ?
