i586 vs i686

[llama-X]

I've scoured the internet for this information, so as a last resort I guess I'll ask here.

The microkernel I'm working on needs a lot of things done in assembly for maximum speed, I want IPC to be lightning-fast in the L3/L4 tradition and the only way to do this is with really specific hardware information.

What are the key differences in the instruction set and in switching from user mode to kernel mode in the Pentium and the P6 instruction set? I suppose info on 486 and Pent differences would be nice too, but... are there even any noticable differences?

In fact, is there anywhere where I can find an itemized breakdown of the differences in the i586 and i686 instruction set?

Thanks! This site is an invaluable resource, and hopefully I can be more than a useless n00b

[Solar]

In the Intel manuals, probably???

[llama-X]

Right, but I can't find the specific Pentium and Pentium Pro manuals, just the current set... I was hoping there was some sort of FAQ I didn't know about... :-\

[Brendan]

Hi,

The microkernel I'm working on needs a lot of things done in assembly for maximum speed, I want IPC to be lightning-fast in the L3/L4 tradition and the only way to do this is with really specific hardware information.

What are the key differences in the instruction set and in switching from user mode to kernel mode in the Pentium and the P6 instruction set? I suppose info on 486 and Pent differences would be nice too, but... are there even any noticable differences?

For a 32 bit OS (i.e. ignoring long mode), for switching from user mode to kernel mode you can use software interrupts or call gates that are the same for all (80386 and later) CPUs. Some CPUs support SYSENTER and/or SYSCALL which are faster, but these depend more on who the CPU manufacturer was than the family.

For IPC (or more correctly, for task switches), the only thing you need to worry about is if the CPU supports FXSAVE/FXRSTOR or if you need to use FSAVE/FRSTOR. For old CPUs (386 and 486) you'd also need to know if an FPU is actually present. There's also an "automatic/delayed FPU/MMX/SSE state save mechanism" that you'd be interested in (to avoid always saving this state during the task switch itself and doing it later if necessary).

As always, check the Intel (or AMD) manuals for full details...


Cheers,

Brendan

[Pype.Clicker]

What are the key differences in the instruction set and in switching from user mode to kernel mode in the Pentium and the P6 instruction set? I suppose info on 486 and Pent differences would be nice too, but... are there even any noticable differences?

You mean like the fact pentium is a 2-pipelines architecture while 486 has only one (and fairly short) pipeline ? like the fact modern pentium are actually RISC cores with a front end that decodes IA-32 instructions into several sub-instructions that can then be scheduled to any of the avaialble N execution units ?

squeezing the max performance from _any_ processor is likely to be quite hardwork, though indeed Intel and Pentium manuals should contain all the timing information, pipelining rules etc. you could need to tune it.

The microkernel I'm working on needs a lot of things done in assembly for maximum speed, I want IPC to be lightning-fast in the L3/L4 tradition and the only way to do this is with really specific hardware information.

Well, you might then be interrested in global pages, cache properties tuning, fast syscall and the like. try to think to your IPC exchanges as a "fast path" and detour anything that cannot be executed in the "fast path" to a more complete (and probably written in a higher-level language) "slow path" handler.

[JAAman]

Right, but I can't find the specific Pentium and Pentium Pro manuals, just the current set... I was hoping there was some sort of FAQ I didn't know about... :-\

you don't need the specific manuals -- the current ones tell you when features were implemented or changed, i havent read the optimization manual but it should contain all the detailed information neccessary to understand optimization on different CPUs

for feature changes, look at the information on CPUID (vol.2a -- pg 3-156 in my rev.16)

[hendric]

Specific manuals? You may pay a visit to intel.com or amd.com.Amd has provided most manuals of its CPU family (I've ever read about them) but Intel has done less.

[Xardfir]

Hiya,

All the manuals are available at this site:
http://www.x86.org/intel.doc/inteldocs.htm

I also highly recommend:
Pentium PRO and Pentium II System Architecture by
Addison Wesley. ISBN 0-201-30973-4

The basic differences can be summarised as follows:

Pentium (i586) was basically a two pipeline i486 with the ability to do two instructions at once.

Pentium PRO (i686) was designed for best 32-bit code performance. As a result 16-bit operating systems (that change their segment registers alot) run slower. Can do up to 5 instructions at once. Pentium PRO also has better mulitprocessing support in hardware.

Pentium II (i686 and a half)? fixed performance and added MMX instructions.

I'm heavily glossing over details here (pipelines, cache location and size, register renaming etc..) Those docs should help, but from a programming point of view a i586 and i686 are virtually identical with the exception of the Machine specific registers (and even most of those are identical).

The one optimization that holds true for all processors past the Pentium Pro is don't alter the segment registers alot. Even a lowly 386 can get a little extra speed by doing this. Apart from that any Pentium specific optimizations should do what they say they do.

[Pype.Clicker]

there are several other "extra features" introduced along the i686 family. CPUID and Model Specific Registers often report the support for those features by the CPU, and CR4 typically enable/disable them.

[Rob]

Okay, first a disclaimer. This is very rough (as in the content and in no site design at all), but I figured I finally needed to get this up on the web.

I've compiled a list of instructions on the x86 platform (didn't have time for x64 yet) and split it up as to which processor/chip it was first introduced with.

Rob's x86 CPU Instruction list

You can view all the instructions, or all of the new instructions for a family or new instructions for a specific processor.

I don't think I'm going to add Itanium (IA-64) or any other instructions from specific cpu manufacturers like AMD or Cyrix (Extended MMX, 3D!Now etc.), but I will add any changes for x64 (AMD64) and registers / flags etc.

Again, this is all very rough, but if you find wrong information or have remarks please do let me know (my name at the bottom of the pages is linked to my e-mail address).

Hopefully it is of some use!

[Pype.Clicker]

Good job

SWAPGS    Swap GS Base Register    
SYSCALL    Fast System Call    P6?

afaik, SYSCALL is an AMD technology and availability is detected through "STAR" MSRs. Should be checked, though.

I don't see any reference to "swapgs" in the books i own about x86 architecture ... that one is x86_64 specific right ? or maybe i'm wrongly assuming that the "complete list" provides a view of "from when any instruction has been introduced" ...

[Rob]

Thanks! It might be that some x64 stuff has already slipped in. I will re-check the full list in the next couple of weeks. If anyone has any definitive info / links on such cases do let me know.

I think SYSCALL is also available on the newest Intel processors that aren't 64-bit, but I could be wrong on that...

[Candy]

Intel only supports SYSCALL in 64-bit mode, and then only as a 64-bit long mode opcode. It does not support it in p-mode.

AMD only supports SYSENTER in 32-bit mode and then only in 32-bit opcode form. It doesn't support it in long-mode.

Of course, this is a bunch of idiocy. Use sysenter in 32-bit mode, syscall in 64-bit mode. That's pretty much all I can figure out from this.

[Rob]

A quick look into the latest Intel manuals from their website indicates SWAPGS is indeed a x64 instruction, as are SYSCALL and SYSRET.

I'll update these three or five instructions shortly

p.s. thanks Candy!

[Rob]

Database has been updated. The 64-bit (only) instructions are listed as new instructions for the x64 extensions, so that's good. I've added remarks that they are only valid in x64 / longmode