tss and user space

[GLneo]

ok, so i use the LTR to put the address of my tss entery in the GDT into the prossesor, right???, but is that the phisycal address or is it the GDT entery number(6)??? <-- can not find anywhere!!! and my GDT entery points to my TSS struct, right??? and if i have to reload the one TSS's registers every task switch, what make software switching fast at all???, thx

[Brendan]

Hi,

ok, so i use the LTR to put the address of my tss entery in the GDT into the prossesor, right???

Yes - LTR tells the CPU which GDT entry to use to find the current TSS.

but is that the phisycal address or is it the GDT entery number(6)???

It's the GDT entry number, for example:

Code: Select all

   mov ax, 6 * 8
   ltr ax

and if i have to reload the one TSS's registers every task switch, what make software switching fast at all???, thx

Software task switching is faster because it doesn't load and save the entire CPU state (only what's needed).

For most OS's, normally some registers are already saved on the stack and don't need to be saved/loaded again, some registers can be trashed (i.e. not saved and reloaded at all) and some things are constants (for e.g. data segment registers might always contain the exact same values).

In addition, a hardware task switch does a pile of protection checks (is the GDT limit too low, is the GDT entry sane, can the GDT entry be accessed at the current privilege level, can the TSS itself be accessed, etc). These checks slow the CPU down and can be avoided with software task switching (where the same TSS is re-used instead of being changed each task switch).

Also, because hardware task switching isn't used much anymore,CPU manufacturers don't optimise the CPU's hardware task switching (instead they optimize more useful things). This makes hardware task switching worse. The same thing can be seen for other "complex" instructions (or instructions that need "microcode" and aren't executed directly by the CPU). For example, "loop somewhere" is actually slower than "sub ecx,1; jne somewhere" on most modern CPUs, even though you'd expect one instruction to be faster than 2 seperate instructions that do the same thing.


Cheers,

Brendan

[GLneo]

ok thx, Brendan, finaly some strait answers ok ive got every thing ready (the Task State regdister points to GDT witch points to TSS struct)but what do i fill the TSS struct with (kernel state, task state) and do i have to refill it every switch???,thx

[Phugoid]

From the description of the LTR instruction:

The source operand (a general-purpose register or a memory location) contains a segment selector that points to a
task state segment (TSS). After the segment selector is loaded in the task register, the processor uses the segment selector to locate the segment descriptor for the TSS in the global descriptor table (GDT).

That reads like a straight answer. There are many more in volume III, chapter 6.

[GLneo]

so if the tss stores the task state, why do i need it if i do software switching, just for the return address???so do i ever need to change the tss values??? does the cpu even look at the tss if i do software switching???

*starts to wish he was osdeving with ppc*:)

[Candy]

... in volume III, chapter 6.

Of what? Intel manuals? AMD manuals? Harry Potter series?

[Phugoid]

That should be clear to anyone who has read the whole thread.

[Phugoid]

so if the tss stores the task state, why do i need it if i do software switching, just for the return address???so do i ever need to change the tss values??? does the cpu even look at the tss if i do software switching???

*starts to wish he was osdeving with ppc*:)

You need it if you have user mode tasks. When the CPU switches to supervisor mode from user mode, it loads the stack pointer and stack segment selector from the TSS. This is how the CPU "remembers" where the supervisor stack was located before the switch to user mode - after all, user mode tasks are not allowed to change this, since that would break protection. Whether or not you ever need to change these depends on the design of your kernel, but the answer is most likely yes.

[JAAman]

hehehe

being vol.3, and it is talking about system management, not instruction execution, i would guess that it would be the

[holy reverence mode]

Intel manual

[end holy reverence mode]

@CLneo
the only things you need to worry about in the TSS for soft-switching, is the SS:ESP for any used ring - except ring3 (the others should be null -- just in case...)
and
the IO protection bits (if you use them -- you don't have to)
and
the IST fields (if you use them -- only applicable in LMode)

[GLneo]

ok, so how should i fill my tss??

Code: Select all

void fill_tss()
{
    TSS->backlink = 
    TSS->__blh = 
    TSS->esp0 = 
    TSS->ss0 = 
    TSS->__ss0h = 
    TSS->esp1 = 
  // ...
    TSS->__fsh = 
    TSS->gs = 
    TSS->__gsh = 
    TSS->ldt = 
    TSS->__ldth = 
    TSS->trace = 
    TSS->bitmap = 
}    

how do i use inline asm to fill these??,thx

[Brendan]

Hi,

how do i use inline asm to fill these??,thx

Fortunately, you don't need to fill them all. All you really need to do is set "TSS->esp0", "TSS->ss0" and "TSS->bitmap".

For these, SS0:ESP0 should point to the top of the kernel's stack for the current task, and "TSS->bitmap" should probably be 0xFFFF (higher than the limit of the TSS, so that the CPU knows that there is no I/O bitmap).

IMHO this should be done in C if you're using C for most things...

Once the initial TSS is setup, you'd just change "TSS->esp0" during every task switch (if each task has it's own kernel stack). That way the CPU knows what to put in SS:ESP when the CPU shifts from user-level to supervisor-level, which is all the TSS is really used for with software task switching.


Cheers,

Brendan

[GLneo]

thx, this is an unrelated question. if i do this:

Code: Select all

struct tss_t TSS;

do i have to access data like this:

Code: Select all

TSS->esp0

or this:

Code: Select all

TSS.esp0

???

[Kemp]

Pointers use ->
Simple (and not so simple) variables use .

So you would use .

[GLneo]

thx kemp, ok i've got this:

Code: Select all

00006409821i[CPU  ] -----------------------------------
00006409821i[CPU  ] selector->index*8 + 7 = 47
00006409821i[CPU  ] gdtr.limit = 23
00006409821i[CPU  ] fetch_raw_descriptor: GDT: index > limit
00006409821i[CPU  ] | EAX=00000028  EBX=00007a00  ECX=00000005  EDX=00000005
00006409821i[CPU  ] | ESP=0008ffdc  EBP=0008ffe8  ESI=00000000  EDI=0000739c
00006409821i[CPU  ] | IOPL=0 NV UP EI PL NZ NA PO NC
00006409821i[CPU  ] | SEG selector     base    limit G D
00006409821i[CPU  ] | SEG sltr(index|ti|rpl)     base    limit G D
00006409821i[CPU  ] |  DS:0010( 0002| 0|  0) 00000000 000fffff 1 1
00006409821i[CPU  ] |  ES:0010( 0002| 0|  0) 00000000 000fffff 1 1
00006409821i[CPU  ] |  FS:0010( 0002| 0|  0) 00000000 000fffff 1 1
00006409821i[CPU  ] |  GS:0010( 0002| 0|  0) 00000000 000fffff 1 1
00006409821i[CPU  ] |  SS:0010( 0002| 0|  0) 00000000 000fffff 1 1
00006409821i[CPU  ] |  CS:0008( 0001| 0|  0) 00000000 000fffff 1 1
00006409821i[CPU  ] | EIP=0000182a (00001827)
00006409821i[CPU  ] | CR0=0x60000011 CR1=0x00000000 CR2=0x00000000
00006409821i[CPU  ] | CR3=0x00000000 CR4=0x00000000
00006409821i[CPU  ] -----------------------------------

when i test in bochs, i think it has something to do with this:

Code: Select all

_setup_tss:
     push ax
     mov ax, 5 * 8 ;GDT #5
     ltr ax
     pop ax

[kataklinger]

Bad limit ( 24 bytes = 3 descriptors ) value for GDT.