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void paging_init()
{
unsigned long counter;
unsigned long temp;
unsigned long *page_directory; //[PAGE_TABLE_SIZE-1]; /*First Page Directory (4096 bytes)*/
unsigned long *page_table_kernel; //[PAGE_TABLE_SIZE-1]; /*Maps in the kernel*/
/*Set up our page tables and directories to their physical addresses: - warning - incompatible assignment types*/
*page_directory= (long *)0x00110000;
*page_table_kernel= (long *)0x00111000;
/*Fill up all tables and directories:*/
for(counter=0; counter<1024; counter++)
{page_directory[counter]=0 | 2;
page_table_kernel[counter]=(counter * 4096) | 3;
}
page_directory[0]= 0x00111000 | 3;
page_directory[512]= 0x00110000 | 3;
/*Enable paging:*/
write_cr3(0x00110000);
get_cr0(temp);
temp=temp | 0x80000000;
write_cr0(temp);
asm("cli");
asm("hlt");
}
Ok, this is what my code looks like now, there is STILL the bug there was before (i.e page fault resulting in triple fault) I suppose I ought to post some of my debugging info so far:
registers are all as they should be as far as I can see:
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00000850940i[CPU ] protected mode
00000850940i[CPU ] CS.d_b = 32 bit
00000850940i[CPU ] SS.d_b = 32 bit
00000850940i[CPU ] | EAX=00100baa EBX=000000ab ECX=000ab000 EDX=0000ffe4
00000850940i[CPU ] | ESP=0000ffcc EBP=0000ffe4 ESI=e0000011 EDI=00000005
00000850940i[CPU ] | IOPL=0 NV UP DI NG NZ NA PO NC
00000850940i[CPU ] | SEG selector base limit G D
00000850940i[CPU ] | SEG sltr(index|ti|rpl) base limit G D
00000850940i[CPU ] | DS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000850940i[CPU ] | ES:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000850940i[CPU ] | FS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000850940i[CPU ] | GS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000850940i[CPU ] | SS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000850940i[CPU ] | CS:0008( 0001| 0| 0) 00000000 000fffff 1 1
00000850940i[CPU ] | EIP=001006cb (001006cb)
00000850940i[CPU ] | CR0=0xe0000011 CR1=0x00000000 CR2=0x0010195c
00000850940i[CPU ] | CR3=0x00110000 CR4=0x00000000
Inserting a 'NOP' opcode before the 'hlt' and 'cli' does NOT change the faulting address in CR2 (so there can't be a problem with those instructions).
Stack is at 0xFFFC
Entire OS is EXACTLY 4.00 kb (no overlap there)
-Changing other bits of code around:-
I've tried changing the order I do things in around (load paging before PIC, IDT and GDT (before it was after)), some of the registers change, but the same error still occurs:
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00000854267i[CPU ] protected mode
00000854267i[CPU ] CS.d_b = 32 bit
00000854267i[CPU ] SS.d_b = 32 bit
00000854267i[CPU ] | EAX=db6f0802 EBX=000003ff ECX=003ff000 EDX=0ee0ffe0
00000854267i[CPU ] | ESP=0000ffcc EBP=0000ffe4 ESI=e0000011 EDI=00000005
00000854267i[CPU ] | IOPL=0 NV UP DI NG NZ NA PO NC
00000854267i[CPU ] | SEG selector base limit G D
00000854267i[CPU ] | SEG sltr(index|ti|rpl) base limit G D
00000854267i[CPU ] | DS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000854267i[CPU ] | ES:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000854267i[CPU ] | FS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000854267i[CPU ] | GS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000854267i[CPU ] | SS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00000854267i[CPU ] | CS:0008( 0001| 0| 0) 00000000 000fffff 1 1
00000854267i[CPU ] | EIP=001006cb (001006cb)
00000854267i[CPU ] | CR0=0xe0000011 CR1=0x00000000 CR2=0x00000040
00000854267i[CPU ] | CR3=0x00110000 CR4=0x00000000
So - I can see no reason why there should be a problem here. If anyone spots anything in the above code, please reply!
I'll post an attachment containing my OS'es source so far (makefiles included), along with my bochsrc and bochsout (included in the 'bin' directory). It may be hard to find your way around, so I'll tell you: the main kernel sources are located in '/src/core/kernel/'
Thanks so much to everyone who's helped so far, an also to those who can see what's wrong with this crazy thing,
OScoder