stack swapping - setting TR

[pradeep]

I have studied multitasking in Distant voices. I am not quite sure of how to setup the Task Register. In my case an invalid TSS exception is happening when i tried to IRET.

I am not quite sure about setting the TSS. I filled just the CR3 and ESP0 field. should i fill SS0 and anyother fields.

A dumb question : What will be on the kernel stack?

Code: Select all

initialize_task:

mov   ebp,esp
push   dword 0x0202
push   dword 0x8
push   dword user1_task
push   dword 0
push   dword 0
push   dword 0
push   dword 0
push   dword 0
push   dword 0
push   dword 0
push   dword 0

push   dword 0x10
push   dword 0x10
push   dword 0x10
push   dword 0x10

mov   [process_esp],esp
mov   [process_ss],dword 0x10
mov   [process_kstack],ebp
mov   [process_ustack],dword USER_STACK

mov   eax,sys_tss
mov   word [gdt_TSS+2],ax
shr   eax,16
mov   byte [gdt_TSS+4],al
mov   byte [gdt_TSS+7],ah

mov   eax,cr3
mov   [sys_tss_cr3],eax
mov   eax,esp
mov   [sys_tss_esp],ebp

mov   ax,TSS_SEL
ltr   ax

pop   gs
pop   fs
pop   es
pop   ds
popad

iret

[pradeep]

When i do an IRET bochs says that the TSS selector points to an invalid TSS. What are reasons for an invalid tss?

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TSS_SEL         equ   $-gdt
gdt5:   dw   sys_tss_end - sys_tss - 1
   dw   sys_tss
   db   sys_tss >> 16
   db   0x89
   db   0
   db   sys_tss >> 24

in TSS i have filled ESP0 , CR3 and SS0

[bluecode]

hi,

I think you have to set the 386bit in your descriptor (byte 7 bit 6).

so the descriptor looks like:

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gdt5:   dw   sys_tss_end - sys_tss - 1
   dw   sys_tss
   db   sys_tss >> 16
   db   0x89
   db   0x40 ;<----that's it
   db   sys_tss >> 24

[pradeep]

Code: Select all

 00001007790i[CPU  ] iret: TSS selector points to bad TSS 

This is the error returned by bochs every time when i do an IRET.
Blue code thanks for ur reply but it doesn't help.

What are reasons for this bad tss ? I think TSS is used only when CPL3 -> CPL0. But in my case CPL0 -> CPL0 . It is not going to use SS0,ESP0 or any other field in TSS. So TSS selector can point in any memory which is present.

In my case before doing IRET in the TSS selector the busy TSS field is set. When does this fileds get set? however this is not reason for bad TSS since busy 386 TSS is also valid.

should the selector be filled with logical / linear / physical address? In my case logical = linear. I filled with this address?

Is there anything i don't understand ? I am stupid at most of the times but here i couldn't figure out that

[bluecode]

should the selector be filled with logical / linear / physical address? In my case logical = linear. I filled with this address?

If I understood you correctly, then your making a fundamental mistake. The task register doesn't take an address. it takes a selector. This selector must be the index in the gdt.
So what's TSS_SEL?

[pradeep]

should the selector be filled with logical / linear / physical address? In my case logical = linear. I filled with this address?

The task register doesn't take an address. it takes a selector

I have been using the term 'selector' for 'descriptor' more oftenly. thanks for pointing out that. But anyway i am filling the TR with the selector of the TSS descriptor. LTR instruction is successful

[distantvoices]

Hehe, that tut of mine is in use *gg*.

Ok: kstack - the kernel stack - is a thing by me. You don't need it, you can use it: switch the stack away from the ring0 stack of the task so there isn't anything munged - just to make sure, nothing wild.

the cr3: I'd avoid writing it in each and every task switch (and especially, writing it in the system tss won't effect anything, eh?). I'd test the value in cr3 against what is stored in the TCB as cr3 value: only if the cr3 of the new task differs from the current cr3 we are to reload cr3 - explicitly by writing the value into the register. Writing it into the system tss doesn't affect anything. The cpu only looks for espn/ssn V n E {0,1,2,3} into the tss in case of privilege transition when you 're doing an interrupt or system call. Hope I've got this right, need to brush up with Intel System programmer Manual ere posting such stuff. *gg*

If questions arise - just ask away.

stay safe

[pradeep]

Yes you are correct i am not able to understand the intel manual becoz my mother tongue is tamil . Have you heard of it?
Any way I couldn't find the reasons for bad tss in intel manual?
can the tss desciptor point to anywhere in valid memory? in case of transition from CPL0 -> CPL3.

[distantvoices]

Well, as far as I remember, the address in the tss descriptor points to the beginning of a tss structure you place somewhere in valid memory - i.e. mapped in memory, if you 've activated paging.

So, in case you insert an invalid pagedir in cr3, or an insufficient filled in pagedir - then a triple fault is likely to occur - or the cpu (bochs) marks, that it isn't able to locate the tss - which is invalid tss.

So make sure that your tss is mapped in in case you are using paging.

second, stick said address into the tss descriptor, and this descriptor you have to stick into the gdt. as simple as this.

As for tamil ... isn't that lingo spoken somewhere in India? Well, my native tongue is german, so we *might* share some lingual roots of old. *rofl*

[pradeep]

yes da machi ! It's spoken in tamil nadu, india.

i finally figured out by myself, at the very beginning of my code i some how messed up and set IOPL=3 So when i change from IOPL=3 to IOPL=0, during IRET it's causing invalid tss error.

Let me know what's happening in this case?
Even if i use EFLAG with IOPL=3 , IRET causes an error.
Is cpu expecting an IOPL map here?