ATA Chipset: Working in PIO mode 3-4, UDMA

[Trashey]

Hello,
in order to work in PIO mode 3/4 (using INSD/OUTSD) there is a need to setup the host chipset (which can be PCI/ISA based) to work at the correct PIO timing value and to support 32bits reads/writes; linux does this by having a driver for each major chipset which is certainly not an option for a hobby OS project.

(A similar chipset timing configuration is needed in order to work in the -advanced- DMA/ULTRA DMA modes except then the read/write is DMA based and not port based.)

However with the enhanced disk drive INT 13 BIOS interface (EDD) there is a possibility to set the working PIO / DMA mode via the SET HARDWARE CONFIGURATION function 0x4E.

At first it seems logical that this can only be used for the INT 13 services, however since setting PIO/DMA beyond mode 2 (other than writing the correct ATA setup command) involves chipset configuration is it safe to assume that the chipset will be configured globally and from then on the ATA device can be accessed as if it was in the correct PIO/DMA mode set by the INT13 service?

If not, is there any way to use the BIOS to set the ATA bus timing? or perhaps is there a generic chipset reference to set all of the above? (except writing a driver for each OEM chipset).

From www.ATA-ATAPI.com:
"The ATA/ATAPI PIO data transfer path via the ATA/ATAPI Data register is only 16-bits wide. The x86 REP INSD and REP OUTSD can not be use directly with an ATA or ATAPI device. However, ATA host adapters are becomming more complex and many of the ATA host adapters that are attached to a 32-bit bus, such as a PCI bus, now support transfering data in 32-bit chunks. This requires that the ATA host adapter have extra hardware to assemble two 16-bit words into a single 32-bit double word and to disassemble a 32-bit double word into two 16-bit words.
This hardware is most likely not enabled in the host adapter at power up. The system's BIOS or an OS device driver is normally required to enable this hardware. However, once this hardware is enabled, then it should be possible to use the REP INSD and REP OUTSD instructions to transfer data. In this case the ATA host adapter must generate two 16-bit INSW or OUTSW I/O cycles to the ATA Data register for each 32-bit INSD or OUTSD I/O cycle that the x86 executes."

Has anyone written a device that supports PIO mode 3 and 4?
Thanks.

[Trashey]

Sorry to bump this up but really nobody knows an answer to this question?

[Brendan]

Hi,

Sorry to bump this up but really nobody knows an answer to this question?

I'd assume that no-one knows for sure, which probably puts you in the unique position to become a pioneer - try the EDD method and see if it works, and perhaps download and compare some chipset docs. If you do find a viable method let us all know and we'll all be gratefull ...


Cheers,

Brendan