Multi-CPU stuff

[FlashBurn]

Ok, back on this topic

I just finished with the rewrite of the detection code for multi cpu and multi io-apics. There are 2 things I like to know. I only support systems >= P-PRO (global pages, 4mb pages, local apic) and I?m now on the point where I need to init the default 2-cpu systems when there is no special MP configuration table. Are there any systems that use this with my system requirements?

Is there any good reason for also implementing acpi for smp detection?

[Brendan]

Hi,

I only support systems >= P-PRO (global pages, 4mb pages, local apic) and I?m now on the point where I need to init the default 2-cpu systems when there is no special MP configuration table. Are there any systems that use this with my system requirements?

AFAIK no. 80386 didn't handle multi-CPU and the MP specification was introduced during the 80486 era. The were some crappy multi-CPU Pentium systems that ignored the MP specification, but these were proprietory things that I'd consider "non-PC compatible" (Compaq did a few of these, but weren't the only ones). For Pentium-Pro and later you can assume that there are no multi-CPU computers without it (at the moment - see below).

Is there any good reason for also implementing acpi for smp detection?

If you want to support NUMA properly then you must scan the ACPI tables (look for an "SRAT" table). NUMA computers (AMD dual-socket) will work without this though - it's mostly for memory management optimization.

However, ACPI is meant to replace the MP specification tables eventually. Every modern (year 2000 or newer) computer I've seen has both, but Windows and Linux both use ACPI. A BIOS manufacturer could consider it optional, especially if they're running out of space in their ROM.

In general I'd look for ACPI, and then if that's not present look for MP specification tables, and if that's not present either assume it's a single-CPU computer. If you skip the ACPI part it should still work fine (I'm not sure when BIOS manufacturers will omit the older tables, but AFAIK none have yet).


Cheers,

Brendan

[FlashBurn]

I fixed all problems I know so that all things are working in Bochs now I want to fix the problems that occure on my dual machine. When I want to start the 2nd cpu I sent a startup msg with this code:

Code: Select all

NO_SHORTHAND= 00000000000000000000b
TRIGGER_EDGE= 0000000000000000b
LEVEL_ASSERT= 100000000000000b
DEST_MODE_PHYS= 000000000000b
START_UP= 11000000000b

mov eax,[act_apicid]
shl eax,56
CALL apic_write_icr, eax, dword (NO_SHORTHAND or TRIGGER_EDGE or LEVEL_ASSERT or DEST_MODE_PHYS or START_UP or 23h)

Code: Select all

;----------------------------
PROC apic_write_icr, highdword, lowdword
;----------------------------
BEGIN
   mov edi,APIC_BASE_ADDR
   mov eax,[highdword]
   mov ebx,[lowdword]
   mov [edi+apic_regs_t.icr_32_63],eax
   mov [edi+apic_regs_t.icr_0_31],ebx

   RETURN
ENDP
;----------------------------

After that the 2nd cpu should run my smp startup code and the bsp goes into a spinloop waiting for the 2nd cpu to get into the kernel. The problem that occures now is that I get an error int from the apic, but there are no bits set in the error register!?

Is something wrong with the msg I?m sending? - in bochs it does work and the apic id is also the right one - Or should I try to resend the msg?

[Brendan]

Hi,

Is something wrong with the msg I?m sending? - in bochs it does work and the apic id is also the right one - Or should I try to resend the msg?

Depending on which CPU and manufacturer there's a different "minimum" sequence for starting the other CPUs. The good news is that there's a single algorithm that works for everything. The algorithm is:

Code: Select all

BSP sends an INIT IPI
BSP delays for 10 mS
IF (APIC version != 82489DX) {
    BSP sends STARTUP IPI
    BSP delays for 200 uS
    BSP sends STARTUP IPI
    BSP delays for 200 uS
}
BSP verifies that it worked

Your problem is probably caused by sending the STARTUP IPI without a preceding INIT IPI.

For more information, read through Intel's Multiprocessor Specification - specifically section B.4 "Application Processor Startup".

Please note that the "82489DX" mentioned above is a local APIC that isn't built into the CPU (it's a seperate chip on the motherboard), and was only ever used for 80486. The 82489DX chips work a little different , have different bugs, etc, and are probably not worth supporting because of this (even if your OS does support single-CPU 80486). I tried to find a multi-CPU 80486 computer on eBay for about a year and gave up. I couldn't find a multi-CPU Pentium either, but everything from Pentium to Pentium III is very similar as far as multi-CPU stuff goes, so there's no real reason not to support it.

BTW I think Bochs works enough for correct initialization code to work, but not enough to stop incorrect code from working too ...


Cheers,

Brendan

[FlashBurn]

Thanks, that was the reason why the statup didn?t work. I was misinterpreting the multiprocessor manual with the init ipi

So now all I need to do is initing the io-apic. Here is the problem that the information I have are not enough to do that. I have the io-apic manual but this is not enough! I will have a look at the linux source and maybe other open source os?s which supports smp.