In my previous posts I have asked for methods on setting up my GDT and gotten great responses (thanks). Now to further aid my descision, I want to know what the Global Descriptor Table does exactly. Heres how I think of it
It provides a set of rules for the offset (ring0, ring3, limit, etc..)
So say you have your code segment with 0x08 being the selector
0x08:(anything between 0 and 4GB) will have the rules applied to it, correct?
Same would apply to other entries in the GDT only with a different selector.
I thought this out a lot and would like to know if this is how it actually works so I can begin to think of how it might be useful in my kernel thus deciding how I'm going to implement the GDT.
Regards,
Warrior
Understanding the Global Descriptor Table
Re:Understanding the Global Descriptor Table
The GDT Entries (Segment types) are 32bit versions of the 16bit segments. As such each includes an offset and length in linear memory (on top of paging). Generally only a flat model is used, Offset=0, Length=FFFFFFFF however as it is simpler.
jmp 0x8:0x10000 will load CS with GDT Descriptor 1, the rules in the GDT Descriptor will applied to all memory accessed via the CS register (which is what the CPU uses when reading and executing code), loading DS and ES means that any accesses via those registers are affected by the applied rules:
Unfortunately, it isn't a question of whether or not it's useful as most people believe it isn't, including AMD who have all but removed it from AMD64, it is necessary for task switching and managing rings, that said, it is usually a "set and forget", you create it at startup [Kernel Code, Kernel Data, User Code, User Data, a TSS for each CPU] then never modify it again (although kernel code continually swaps segment registers in places like the interrupt handlers).
jmp 0x8:0x10000 will load CS with GDT Descriptor 1, the rules in the GDT Descriptor will applied to all memory accessed via the CS register (which is what the CPU uses when reading and executing code), loading DS and ES means that any accesses via those registers are affected by the applied rules:
Code: Select all
mov eax, 0x10
mov ds, eax
mov eax, [ds:0x4500] ;Equivalent to "mov eax, [0x4500]"