About selector

[gaiety]

I am now learninng about protected mode, if I am setting a GDT and siwtch to protected mode. Let say I am putting a code descriptor entry at 0x08 and data at 0x10.

for accessing address in protected, my CS has to be 0x08, Is it the selector is 0x08? and it should put in CS?

#2 question, if 0x08 is a selector, the selector format I found is like these,

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15   14   13   12   11   10   09   08   07   06   05   04   03   02   01   00
[         Pointer into a Descriptor Table         ]   TI   [ RPL ]

Why my selector don't need to put RPL and TI bit to be set?
should it be

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selector = 0x08 << 3 + TI << 2 + RPL
_CS = selector

but the needed is just put 0x08 into _CS and everything OK. so why is it. Or the selector is not 0x08.

#3 question, what is cascade for PIC. I check for the dictionary and it talk about waterfall, so what is it about?
I have a lot of question about cascade.

[fraserjgordon]

Question 1:

Yes, you do put 0x08 into CS. To do this, use a ljmp assembler instruction.

Question 2:

If TI is set, the selector refers to the local descriptor table and not the global one. Most people ignore the local table now. The RPL is the Requested Privelege Level and as you are writing the kernel, this is 0 so leave it unset.

Question 3:

"Cascaded" means that the PICs are connected together on one of the IRQ channels (IRQ2 IIRC). Luckily, programming two PICs isn't too much more difficult than programming one. I think there is a tutorial on it somewhere on the Wiki.

[gaiety]

I am ready a beginner, I see some article that to write an OS needed to understand everything you wrote but not to assume it. So for the cascade, I have read the wiki and some other material, but I have a few question.

#1

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remap_pic(0x20, 0x28);

It will be use to remap the interupt from 0x20 to 0x2f, why it is not puting 0x2f instead of 0x28.(Like baby question.)

#2 If we remap the start address at 0x20, will it mean that the first IRQ map will be 0x20 in IDT. Second will be 0x21. However, for IRQ 8, will it is in 0x28 or needed to do something with IRQ 2.(I only know how to do for keyboard and timmer so far.)

#3 For example, if I have reprogram the interupt at 0x20, for keyboard, will the interupt 0x09 stop functioning.

#4 When masking for the interupt by outport mask to 8259A chip, for example, 0xfc for master and 0xff for slave, will the harddisk interupt stop function or they just not map to the interupt that we pointed but still functioning with their "own or orginal" interupt function. (I ready don't know how to exam it if it is functioning.)

#5

"Cascaded" means that the PICs are connected together on one of the IRQ channels (IRQ2 IIRC).

I am ready a beginner, (I guess) if it mean that it cascade the IRQ 0, IRQ 1, and IRQ 3 to IRQ 15 into IRQ 2, then it mean that all the IRQ signal will be send to IRQ 2 and IRQ 2 will send request to processor for interupt acknowledge, then proccessor will excute the interupt process.

I read some matrial that one IRQ line will be reserved for sending signal and will not use, will the reserved line be IRQ 2? (If is, the below is a question) So we can't program the interupt for IRQ 2. For example, I map the interupt with

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remap_pic(0x20, 0x28);

then the IRQ 2 will be the interupt at 0x22, so it should not be program at all. And the mask should always set?

Or the above for the question 5 just get the wrong meaning.

Thank you for answering my question.

[Brendan]

Hi,

#1

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remap_pic(0x20, 0x28);

It will be use to remap the interupt from 0x20 to 0x2f, why it is not puting 0x2f instead of 0x28.(Like baby question.)

The PIC chip will ignore the lowest 3 bits, so you could use 0x28 or 0x2F and it'll be exactly the same. You could use "remap_pic(0x20, 0xF0);" and use IRQs 0xF0 to 0xF8 though..

#2 If we remap the start address at 0x20, will it mean that the first IRQ map will be 0x20 in IDT. Second will be 0x21. However, for IRQ 8, will it is in 0x28 or needed to do something with IRQ 2.(I only know how to do for keyboard and timmer so far.)

Not sure I understood the question, but in order to receive any IRQ from the second PIC chip you will need to unmask the first PIC chip's IRQ 2 - without this the "cascade" won't work.

#3 For example, if I have reprogram the interupt at 0x20, for keyboard, will the interupt 0x09 stop functioning.

The BIOS's IRQ1 handler will stop working, and unless you've got interrupts disabled (or you've got some code to handle the new interrupt number) your computer will probably crash. Generally you'd only remap the PIC chips when you don't need the BIOS anymore (ie. ready to switch to protected mode). Then you'd disable interrupts (CLI), remap the PIC chips, enable protected mode and install your own IRQ handlers (not necessarily in that order, as long as disabling the IRQ's comes first).

#4 When masking for the interupt by outport mask to 8259A chip, for example, 0xfc for master and 0xff for slave, will the harddisk interupt stop function or they just not map to the interupt that we pointed but still functioning with their "own or orginal" interupt function. (I ready don't know how to exam it if it is functioning.)

The devices generating the IRQs still function and still send their IRQs to the PIC, but the PIC doesn't forward them to the CPU. This means some devices will get blocked up. For e.g. the keyboard generates an IRQ when it's got some data in it's buffer ready to send, and the IRQ handler normally gets this data out of the keyboard buffer. If the IRQ handler isn't called (ie. if the PIC has IRQ1 masked) the byte doesn't get taken out of the keyboard's buffer and the keyboard won't be able to put another byte into it's buffer later (even if IRQ1 is un-masked later) - you'd need to reset the keyboard or take the original data out first.

My message was too long so I've split it into 2 seperate messages....

[Brendan]

...continued from last message.

#5

"Cascaded" means that the PICs are connected together on one of the IRQ channels (IRQ2 IIRC).

I am ready a beginner, (I guess) if it mean that it cascade the IRQ 0, IRQ 1, and IRQ 3 to IRQ 15 into IRQ 2, then it mean that all the IRQ signal will be send to IRQ 2 and IRQ 2 will send request to processor for interupt acknowledge, then proccessor will excute the interupt process.

I read some matrial that one IRQ line will be reserved for sending signal and will not use, will the reserved line be IRQ 2? (If is, the below is a question) So we can't program the interupt for IRQ 2. For example, I map the interupt with

Code: Select all

remap_pic(0x20, 0x28);

then the IRQ 2 will be the interupt at 0x22, so it should not be program at all. And the mask should always set?

Or the above for the question 5 just get the wrong meaning.

IRQ 2 is the reserved IRQ (reserved for cascade). Basically older CPUs only had one interrupt pin that was originally connected to a single PIC chip (back 20 years ago). Only having 8 IRQs wasn't enough though so they used 2 PIC chips so they could have more IRQs. This was a problem because the CPU still only had 1 interrupt line. To get around this they connected the second PIC chip's interrupt output to the first PIC chip's IRQ 2 input and put IRQ2 into a special "cascade" mode.

Generally when the first PIC chip's first input (IRQ1) receives an IRQ from the keyboard the PIC chip sets it's interrupt output which tells the CPU there's IRQ data coming, and then the first PIC chip sends the IRQ number to the CPU using the address lines of the CPU's bus.

When the second PIC chip's first input (IRQ8) receives an IRQ from the CMOS/RTC timer it sets it's interrupt output, which is connected to the first PIC chip's second input. The first PIC chip receives this and sets it's interrupt output which tells the CPU there's IRQ data coming, but it does not send the IRQ number because IRQ2 is set in the special "cascade" mode. Instead the second PIC chip sends the IRQ number to the CPU using the address lines of the CPU's bus.

I've overlooked a little "handshaking" for the sake of simplicity, but that's how the PIC chip's still work today. It would be possible for motherboard manufacturers to have up to 64 IRQ lines by using one master PIC and 8 slave PICs (the original "8259" chip was designed to allow this, as well as supporting other/different CPUs), but it wouldn't be "PC compatible" if they did this.


Cheers,

Brendan