Quick question: Paging & IDT

[Mr. L]

Hi,
I have paging enabled with an IDT and it's associated ISRs. I can invoke interrupts but when I do I get a page fault (which doesn't get called).

My question is: to enable ISRs to be called in paging mode, do you have to put them (ISRs) into a particular page frame or into a page with a particular attribute?

Thanks,
Mr. L

[AR]

The ISR function pointers in the IDT are affected by paging, the IDT Descriptor must contain an always valid virtual address for the ISR. You will need to make sure that the page(s) containing the ISRs are mapped in at all times.

[Mr. L]

The ISR function pointers in the IDT are affected by paging, the IDT Descriptor must contain an always valid virtual address for the ISR. You will need to make sure that the page(s) containing the ISRs are mapped in at all times.

I'm pretty sure that I have all my ISR functions mapped within the page area I specified (under 4 MB with exact exact mapping i.e. 0x2250A000 really is 0x2250A000).

The only thing I can think is that maybe my ISR functions span across more than one page frame. Would this cause a page fault because the CPU has to notify you every time you need to access another frame?

[AR]

The CPU is only ment to raise a fault when it can't access a memory address. Are you sure the pages are mapped in, my ISRs cross a page boundary whenever LD feels like linking it that way and I've never had a problem?

It does really sound like the Page Directory and/or Page Table (and/or Segment) isn't set up correctly. It could also be caused by an invalid pointer in the ISR though, do the ISRs make any references to memory outside the space you mapped? (like the stack is in the wrong place, or simply dereferencing a pointer which is outside 4MB)

[Mr. L]

Thanks for the reply AR.

I can assure you that all of my operations are below 4 MB in physical address space (for which I have mapped). My ISR pointers and functions work perfectly without paging enabled so, I know that the problem must be something other than the incorrect configuration of my GDT, IDT and ISRs.

My page directory is located at 0x9C000 and my page table is located at 0x9D000. Do you think think the placement of my paging tables (0x9C000 - 0x9D400) is appropriate? Is this area of memory highly volatile?

Please let me know your thoughts as I am keen to resolve this matter.

Thanks.

[AR]

There doesn't seem to be anything wrong with where you've put them.

(0x9C000 - 0x9D400)

You meant 0x9C000 - 0x9DFFF?

If you're sure the stack is valid then the only other thing I can think of is placing a HLT before the STI then use Bochs to do a trace to see how far it gets and which instruction actually causes the fault.

Without actually seeing how the tables are made I'll suggest you try this code (32 bit NASM Assembly):

Code: Select all

mov ecx, 2048
mov edx, 0x9C000   ;Flush the memory
.ZeroMemoryLoop:
mov dword [edx], 0
add edx, 4
loop .ZeroMemoryLoop

mov dword [0x9C000], 0x9D003   ;Set 0-4mb page table

mov ecx, 1024      ;1024 entries in a page table
mov edx, 0x9D000   ;Page table address
mov eax, 11b      ;Physical Page Address
.GenTable:
mov dword [edx], eax      
add edx, 4      ;Increment to next page table entry
add eax, 0x1000      ;Increment to next physical page
loop .GenTable

mov eax, 0x9C000   ;Load Page directory
mov cr3, eax

mov eax, cr0      ;Enable Paging
or eax, 0x80000000
mov cr0, eax

I know this generates valid tables so if it doesn't stop the problem then your page tables are fine.

[Mr. L]

Thanks a lot AR.

You were right in telling me that my page directory wasn't setup properly. The only difference between your page code and my page code is that in my code I was gratuitously filling in page directory entries. But in doing so I mistakenly overran the page directory and spilled code into my first page table entry.

I will definetly be using your code in place of mine because its smaller and includes a zero memory routine.

Thanks again ;D