TSS and interrupts problem

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Neuromancer

TSS and interrupts problem

Post by Neuromancer »

Hi,
in my OS, i started coding the multitasking subsystem.
I load the TR (ltr) successfully and I switch to a ring0 task successfully, but when I try to enable the timer interrupt and the scheduling system, I see (using GDB) that when the CPU enters the IRQ0 handler, my TSS is totally modified.
The IRQ0 does not issue a context switch, but jumps to a mapped ring0 area (I am sure memory management is OK) so the TSS should not be touched.
What is going on?
If you have understood what I am saying, could you help me? Thanks.
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