Paging: 4k'n'4M mix?

[Nikso]

Hi there!

I'm just implementing paging and my intentions are to enable both 4k and 4M pages. But after the page directory initialization, if I try to set the bits of CR4, cpu have a fault.
Instead, paging work with 4k page but graphic stuff doesn't work.
I don't know how should I do with the linear frame buffer of vesa... it have an address like 0xE0000000!!

Thanks for the help! Bye!

[Brendan]

Hi,

I'm just implementing paging and my intentions are to enable both 4k and 4M pages. But after the page directory initialization, if I try to set the bits of CR4, cpu have a fault.

Which fault, where and mostly why?

Instead, paging work with 4k page but graphic stuff doesn't work.
I don't know how should I do with the linear frame buffer of vesa... it have an address like 0xE0000000!!

You'd map the linear frame buffer (or the display memory in general) into an address space somewhere, in the same way that you'd map any other physical address range.


Cheers,

Brendan

[Nikso]

Well, if I try to enable paging after interrupts initialization, I receive the exception 1! (Debug exception!! o_O)
And bocks give me this error:
#GP(0): SetCR4: Write of 0x00000090 not supported (allowMask=0x0)
This happen when I execute:

Code: Select all

   MOV EAX,CR4
   OR EAX,10010000b ; Enable global and 4MB pages
   MOV CR4,EAX

And I still don't know how to map LFB, I've try the follow with 4kB pages (in pseudocode):

Code: Select all

; index 1 of the pagedir is for kernel page table...
index = LFBAddr >> 22 ; shift is for divide it by 4MB, I do this because graphic functions access to LFBAddr directly so I need a 1:1 proportion in pages (I've also try to edit functions...)
PageDirectoryAdd(index, PageTable2)

addr = LFBAddr OR 3
PageTable2:
for(i=0; i<1024;i++)
{
     Write(addr);
     addr += 4096
}

(What a nice pseudocode )

Thanks, byee

[Dreamsmith]

Did you check the CPUID flags to see if 4MB pages are supported?

[DennisCGc]

Did you check the CPUID flags to see if 4MB pages are supported?

In a "standard" bochs doesn't have support for 4 MB pages....

[Nikso]

LOL so maybe this is the problem... I'll search for a modded bochs ^_^ with visual debug if exist

Thanks

[Therx]

Have you tried it on a real PC? As long as you choose a realitively new PC then that feature will definately be implemented so you can see if it works. I doubt (don't take my word for it) that its possible to break a computer with paging code alone.

Also why do you need a graphical bochs debuger. If you read the online docs learning how to use the text based one is not hard. And if you're planning to write a full OS then its going to be one of the easier things you come across.

Pete

[Candy]

I tried PAE (plus global plus PSE plus all the other nice crap) on a Bochs machine specifically compiled for that, and it tripled. All was properly laid out etc, I triple checked it all (had to be 3 of course), and then tried it on my computer without bochs in between. It instantly worked.

conclusion: Bochs in its 2.1 incarnation cannot properly do PAE paging. Real CPUs can.