delaying

[virusx]

hi,
I have a problem delaying.
The condition for delay is the interrupts are disabled, I cannot use the handler of rtc, pit interrupt.
Of cource Reading seconds field in CMOS and looping till it change does not work because i have already initialized gdt and pic.

thanks

[Ozguxxx]

For single tasking it is ismply counting for correct number of irq0 ticks, for multitasking again count for correct number of irq0 ticks but you should do this in scheduler and for each sleeping task since there can be some number of sleeping tasks. for multitasking case you might need some coding tricks to make process sleep, I needed them but it depends on your design. Why do you need to disable interrupts?

[virusx]

thanks,
But i said
1) interrupts are disabled(i can enable them for short time.)
2) Dont have access to irq handlers

I have seen somebody doing this by looking at some bits of some port.
I think it was 0x61.

Anybody please....

Thanks

[Pype.Clicker]

I have seen somebody doing this by looking at some bits of some port.
I think it was 0x61.

since the CMOS-RTC chip (accessible through ports 0x70 & 0x71) hold the time-of-day including seconds, you might want to poll it until it canged, but that will be of no use for delays < 1s and will be very inaccurate for delays < 10s

Still, you can use the PIT, but in polling mode (polling on the counter): this technique is shortly introduced on the "How do i tell CPU speed" page of http://www.osdev.org/osfaq2/.

Finally
- why can't you enable interrupts ?
- why don't you have access to interrupt handlers ?

If you're not allowed by the CPU to access handlers, you'll be unlikely to be allowed to do anything on I/O ports anyway ...

[virusx]

hi,
Does polling for CMOS seconds field change work after initializing PIT and IDT. I dont think so.

I have interrupts disabled but I can enable.. (ok).

I dont want to count by listening to irq handler.
I need another simple way.

I notices in linux kernel source. It is doing something on counter 2 of PIT(sound generator) and listening to value 0x20 on port 0x61.

/* Set the Gate high, disable speaker */
   outb((inb(0x61) & ~0x02) | 0x01, 0x61);

   /*
    * Now let's take care of CTC channel 2
    *
    * Set the Gate high, program CTC channel 2 for mode 0,
    * (interrupt on terminal count mode), binary count,
    * load 5 * LATCH count, (LSB and MSB) to begin countdown.
    */
   outb(0xb0, 0x43);         /* binary, mode 0, LSB/MSB, Ch 2 */
   outb(CALIBRATE_LATCH & 0xff, 0x42);   /* LSB of count */
   outb(CALIBRATE_LATCH >> 8, 0x42);   /* MSB of count */

   {
      unsigned long count;
      count = 0;
      do {
         count++;
      } while ((inb(0x61) & 0x20) == 0);
...

thanks

[Pype.Clicker]

http://www.nondot.org/sabre/os/files/HC ... ardFAQ.txt
might help you identifying the 'magic' around port 0x61

obviously, the 'Timer2 gate' is activated, but the 'Timer2 data' is cleared, which looks to be some unusual configuration, and the 'channel I/O check' will report what should have been sent to the speaker (a square wave, iirc)

By selecting the value of CALIBRATE_LATCH, you'll be able to wait for any amount of 838ns (the base period of the PIT crystal

[DennisCGc]

hi,
Does polling for CMOS seconds field change work after initializing PIT and IDT. I dont think so.

Why not ?

[srg]

http://www.nondot.org/sabre/os/files/HC ... ardFAQ.txt
might help you identifying the 'magic' around port 0x61

obviously, the 'Timer2 gate' is activated, but the 'Timer2 data' is cleared, which looks to be some unusual configuration, and the 'channel I/O check' will report what should have been sent to the speaker (a square wave, iirc)

By selecting the value of CALIBRATE_LATCH, you'll be able to wait for any amount of 838ns (the base period of the PIT crystal

Wow, I never even knew about port 0x61. What an interesting find, it also has about disabling the keyboard.

I've always wondered how that one timer could be used for both general use or the Speaker.

srg

[virusx]

Ok,
PPi chip. Can you explain what the code is doing. Or at least bit 0:
bit 1:
bit 4:
is doing.
Any pointers will be helpful.

Denniscgc:
Will the CMOS memory gets updated all the time even when kernel takes control over IDT and PIC.
I thought that it stops working that way when we program irq to work our way.

Thanks.

[Pype.Clicker]

all that 'PPI' was used for was controlling some signals to ordinary logic gates (much like the A20 gate) here and there on the initial PC motherboard. you'd need the detailed schematics of an IBM-compliant PC-XT to find out how it actually works, but i don't have that information here...

http://www.motherboard-links.com/diagra ... rd_xt.html looks to be a great mine of informations