LTR doesn't like my TSS descriptor.

[mr. x2]

I think the task doesn't get switched to, I tested to set the T bit to make it raise a debug exception, but it didn't work.
I've tried to set the ESP field in the TSS to 0xDEABEEF and when I get the general protection fault I can see that ESP isn't 0xDEADBEEF.
I've tried to set the base of the TSS Descriptor to 0 and I get the same general protection fault.
How does ljmp know that it should jump to a task? 0x28, 0x0 could be anything.
Should the TSS be located in a special place somewhere?

[Pype.Clicker]

make sure you've read the manuals accurately enough ...
- the base of the TSS descriptor should point to a linear address of a block of memory that holds the TSS content.
- it is better for the TSS to be on a single page. If it spans on multiple pages, make sure a PF on one will load *both*
- the limit should not be smaller than 0x64 bytes (iirc)

do you have the 'error code' and the 'current TSS' (str) at the GPF ?

[mr. x2]

I've finally fixed it, I didn't really understand what the GDT should be pointing to, I had it pointing to an array of TSS's.

I've tried to make the task run as a v86-task, but there's a problem when I try to change graphics mode with int 0x10:
[CPU ] interrupt(): SS selector null

[Pype.Clicker]

I've finally fixed it, I didn't really understand what the GDT should be pointing to, I had it pointing to an array of TSS's.

That was indeed a bad idea ... the GDT should point to an array of descriptors (e.g. the 8-bytes structure with base, limit, type, etc.) and a TSS selectors holds (in its base) the pointer to a TSS structure (which may come from an array, that doesn't matter, actually)

I've tried to make the task run as a v86-task, but there's a problem when I try to change graphics mode with int 0x10:
[CPU ] interrupt(): SS selector null

Just keep in mind that, per se, V86 is not able to execute 'INT xx' instruction. Thus it will report a GPF if any 'priviledged' operation appears (like IN, OUT, INT, etc). Just make sure your TSS has proper SS0 and ESP0 values for handling interrupts and make the GPF handler call the V86 monitor for emulating the priviledged instruction if required...