TSS's

[mr. x2]

I've got software task switching up and running, but now I want to make it run in ring 3. Should I have one TSS (for syscalls), one code segment and one data segment per task?
Can someone point me to a tutorial or help me out in any way... all I find is how I do hardware task switching with TSS's, not how to call ring0 interrupts from a ring3 code segment.

[Pype.Clicker]

you need a TSS, a code and data segment for user mode (which could be the same segment for every process like in Linux though i discourage that approach) and have SS0:ESP0 in your TSS pointing to some valid place where the kernel stack should appear ...

[DennisCGc]

What should be in the TSS, when I use software switching ?
I mean: if I switch to another segment, should CS be changed in the TSS too ?

[Pype.Clicker]

The cs:eip values will be loaded from the interrupt descriptor, so you needen't to worry for them. same for other *s values (they'll either be kept from userworld or reset to some valid kernelworld values) ...

Indeed when switching to another software thread you'll need to take care about saving the current TSS.ESP0 and TSS.SS into some thread-local storage and to restore the values of the next thread in the TSS...

[DennisCGc]

So, if I get it, I should change TSS.ESP0 and TSS.SS0 when switching to ring 3, or not ?
And, when I mean, switching to another CS, I mean a cs selector in ring 3... so, should that be changed or not ?
(sorry, I'm working on multitasking, and doesn't work well :-[ )

[Pype.Clicker]

okay. Let me try to give a comprehensive sketch of what may occur and then tell me what concerns you ...

• entering user mode at first time, which basically consists of placing interrupt-like structure on the stack featuring a userworld code and stack selector and then issueing a iretd instruction.
• handling an INT nn from userworld (system call), which requires a TSS.SS0 and TSS.ESP0 and an IDT entry to have been setup first
• switching from one code segment to another one in userworld, which is transparently performed by a jmp far new_selector:offset and which the OS doesn't need to take care of
• switching from one userworld thread to another userworld thread

[DennisCGc]

Okay, when I run a task in PL 3, it runs fine, so, I implented in the timer interrupt a switching method, which switches the registers from the tasks.
Every task has a seperate stack.
So if the timer interrupt is called, it crashes
Bochs gives GET_SS_ESP0_TSS_TR.cache error (or something alike).
So, what's wrong ?

[Pype.Clicker]

either you haven't loaded TR register with a valid TSS selector, or that TSS has invalid SS0/ESP0 values ... those are used to load SS and ESP when a 'stack switch' occurs due to an interrupt or an exception (should be documented thoroughly in the Intel Manuals

[DennisCGc]

I hope so
Since the Intel Manual is a little bit chaotic (that's what I think )
And I can't find most of the time not the relevant information.
So ... ::)

[Pype.Clicker]

probably a good advice for using the Holy Manuals is to learn the whole Tables of Content before delving into separate chapters