OK, before I triple fault my OS again repeatedly, can somebody tell me, if you enable paging in protected mode, do your GDTR and IDTR need to contain the physical memory location of the tables, or the virtual addresses as mapped by the paging? Also, how about the pointers to your interrupt handlers in the IDT? Should these addresses point to the physical memory location, or to the addresses as mapped where the kernel image is?
Help appreciated,
HuntrCkr
GDT and IDT with paging
-
anton
RE:GDT and IDT with paging
If paging is used, the only physical address that the CPU knows of is in CR3.(In the intel Manual Volume 3 it states:
2.1.5. Memory Management:
...
When paging is used, all the code, data, stack, and system segments and the GDT and IDT can be paged, ...
)
All the entries in the interrupt table are virtual linear address(Interrupt Gate,Trap Gate) or index to task table(Task Gate).
2.1.5. Memory Management:
...
When paging is used, all the code, data, stack, and system segments and the GDT and IDT can be paged, ...
)
All the entries in the interrupt table are virtual linear address(Interrupt Gate,Trap Gate) or index to task table(Task Gate).