Is the PIC related to the system chipset?

[stonedzealot]

Well, that strange Divide by Zero problem (the gist of it is that after implementing the keyboard, the code worked perfectly on two Intel computers but failed on my homemade SiS computer, giving Interrupt 0) from nowhere I was having has returned. Only this time, I find that it is generating completely random interrupts. Here's the thing, I've found two more test computers at a friend's house and this came up:

CHIPSET
SIS --- Failure (Interrupt 0)
SIS --- Failure (Interrupt 0)
NForce --- Failure (Interrupt 47?)


Intel -- Success
Intel -- Success

My friend informs me that Intel is notoriously stable in comparison to other chipsets. So, could the PIC (or really anything) be connected with the chipset that would cause the keyboard/PIC code to fail on anything but Intel chipset computers?

The real test will come tomorrow when I test it on another friend's Intel chipset computer.

[Slasher]

Its your code not the chipset. I have an Nforce chipset motherboard, Intel chipset motherboard and a SIS chipset motherboard. All of them work with my PIC code and Interrupt handlers.
No PC company will release chipsets that are not compatible with the IBM PC.
So you hve to go over your code.

[stonedzealot]

I'm not suggesting that they're incompatible, I'm suggesting that perhaps the Intel chipset assumes some things that other chipsets don't by default so I need to initialize them or something. I dunno. I'm really just grasping at straws, I know. I mean...the codes got something wrong with it obviously (as it doesn't work) but I have no idea why and I noticed that it works on all of the Intel sets that I test it on.

[stonedzealot]

Actually, now I've figured it out. I think it must be the chipset. Because: I was accidentally telling the PIC's ICW3 two different numbers for the connecting IRQ line and as far as I can tell the Intel chipset boards said: "Hey these two numbers need to be the same" and changed the Slave PIC's number to the Master PIC's to make everything fine and dandy. My guess is that other chipset's PIC's had no such sanity check (while retaining compatibility)

[Tim]

That wouldn't be surprising. A lot of chipsets don't bother implementing features that mainstream OSes don't use. For example, few modern floppy disk controllers support PIO mode, even though the original spec defines a PIO mode. It sounds like you're using some obscure feature of the PIC and expecting it to work everywhere.

[Curufir]

Fun bug to catch, but imagine if you'd assumed bad hardware and left it until later...

Would still be interesting to know why you were getting int 0 though, unless screwing up the cascade somehow resets the interrupt vectors.

[stonedzealot]

Actually, I wasn't trying to implement anything weird, I just made a very stupid mistake =).

As for that divide by zero thing, I have a feeling that's just the computer getting very confused and issuing the first error it can think of. The one that really seems odd if the NForce's int 47...that's not bound to anything...