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With PAE does the page-directory-pointer-table have to be inside the first 4gb of memory as the field in CR3 for its address is 27bits long and the intel doc says:-
This field provides the 27 most-significant bits of the physical address of the first byte of the page-directory-pointer table, which forces the table to be located on a 32-byte boundary.
Surley if it could be any where up to 64gb then it would still be aligned by 2kb with the 27bit field
Pete wrote:
With PAE does the page-directory-pointer-table have to be inside the first 4gb of memory as the field in CR3 for its address is 27bits long and the intel doc says:-
This field provides the 27 most-significant bits of the physical address of the first byte of the page-directory-pointer table, which forces the table to be located on a 32-byte boundary.
Surley if it could be any where up to 64gb then it would still be aligned by 2kb with the 27bit field
Pete
Yes for intel PAE, No for AMD 64-bit PAE.
It can only be in the first 4G, aligned to a 32-byte boundary.
PS: If you want some PAE code that (I believe) works, my project should be working with PAE on normal processors now. www.sf.net/projects/atlantisos. Cannot get it to work on bochs though.....
