interesting paging problem

[Ozguxxx]

Heres the problem: I load kernel to 1 Meg, which is formerly mapped onto itself, I mean first 4Meg is mapped onto itself, after that I map 3 Gig onto 1 Megabyte as in 1:1 scheme, and when I unmap first 4 meg onto itself, one page from 1Meg to 1Meg+4K still seems to be present, well how is this possible. To be more clear:

1) Load kernel on 1 Meg
2) Set a page table so that 3Gig to (3Gig + 4Meg) is mapped onto 0 to (0 + 4Meg)
3) Set a page table so that 0 to (0 + 4Meg) is mapped onto 0 to (0 + 4Meg)
4) Enable paging. (I know that this is correct.)
5) unmap mapping done at 3rd step by setting first entry in page directory to 2.
6) At this step when I test by trying to get a value from 1Meg upto (1Meg + 4Kbytes) no page faults occur which is I think impossible, however all addresses other than these in first 4 Megs give page faults as expected.

I dont understand, I need some guru advice. Thanx.

[Carnac]

You also need to enable the A20 gate.

[Perica]

..

[Ozguxxx]

Carnac: I am 100% sure that a20 is on.
Perica: Although I havent tested thoroughly yet, problem seems to be in tlb flushing... this will be an easy answer but does anybody know how many entries does tlb store? ;D
BTW, thanx Perica, I think I could not find this error for at least a couple of days before asking here...

[Pype.Clicker]

the amount of TLB entries usually depend on your processor ... maybe looking at the CPUID cache informations could help ... i dunno if they are listed there or not ...

[Perica]

..

[Pype.Clicker]

Why does it matter how many TLB entries the CPU has? Just execute an invlpg instruction for every page that you unmapped.

you can also flush them all at once by reloading CR3...

[Ozguxxx]

or doing a task switch (I know this is a stupid method... )

[Candy]

or do INVD or WBINVD...

[Pype.Clicker]

or do INVD or WBINVD...

hmm. maybe i need to refresh my mind with 486 instructions, but isn't "INValiDate" and "Write Back INValiDate" instruction just flushing the *data* cache ? i'm unsure they'll be able to change the translation lookaside buffers, which are a separate caching area with a separate control mechanism ...

[pini]

Remainder :

INVD invalidates and empties the processor's internal caches, and causes the processor to instruct external caches to do the same. It does not write the contents of the caches back to memory first : any modified data held in the caches will be lost.

WBINVD invalidates and empties the processor's internal caches, and causes the processor to instruct external caches to do the same. It writes the contents of the caches back to memory first, so no data is lost.

Now the question is : Is TLB part of "internal caches" ?