Is this possible? :
I load in the TR the offset of a TSS, the TSS points to a virtual address, that is translated using paging. If I load a new set of pages, in which the TSS address points to a different TSS, will the CPU be fooled and thus use the new TSS for the stack pointers etc? (as in, for the CPL3 stack pointer)
Can I enable pmode & paging in one go? I mean, can I load the page table & pmode in realmode and then do a far jump to the paged virtual address to start it off? Does that work or do I need to be in PM to do such a jump?