MMX and SSE/SSE2 task switch

[FlashBurn]

I want to make my scheduler mmx/sse/sse2 compitable. So I do the following steps:

-setting the bit 5 in cr0
-setting the bit 17 in cr4

And in my pit handler I do this:

-sub esp,512
-fxsave [esp]
And at the end:
-fxrstor [esp]
-add esp,512

But when I test it under Bochs it gives me a 3rd exception!

What make I wrong?

[FlashBurn]

OK, I fixed the problem with the FPU state! I have to do an fninit before I use a FPU command. But the thing still don?t work for mmx!

Say if I?m wrong.

When I only want to save the FPU state I have to use fsave, but If I want to save the MMX state I have to use fxsave and before this I have to set the 17th bit of cr4 and the 5th bit of cr0. So what make I wrong that my real PC restarts and Bochs says set I need to enable sse to use the fxsave command?

[bkilgore]

Did you try finding out which line exactly bochs is having a problem with? That might help...

[FlashBurn]

Boxhs has a problem with the fxrstor and fxsave opcodes! It says that I should use the parameter --enable-sse.

I?ve read one more time the intel manual 3 and now I do the folowing steps, which should make it possible to save the fpu and mmx state with fxsave:

-test if mmx and fxsave and fxrstor are avaiable
-set the 5th bit of cr0 and clear the 1st and 2nd bit of cr0
(I count the bits beginning with 0!)

This should be enough for only saving the mmx state when using the fxsave command. But it doesn?t work either in Bochs nor on my real PC

[bkilgore]

I don't know about the enable sse option, but do you need the [] around esp in your code? Isn't esp already an address?

[FlashBurn]

Yeah, because if I don?t do that NASM want compile it. Also esp is not an address but its value is an address!

[Pype.Clicker]

note: after a task switch (if you perform task switches), the 'TS' bit needs to be cleared with the special 'CLTS' instruction to tell the processor that the FPU is restored and can be used. If you use the FPU (including for FXRSTOR) before you CLTS, you'll get a "coprocessor not present #7 EXC". And if you have no handler for this one, you'll eventually encounter a tripple fault ...

[bkilgore]

I was looking it up online, and I came across this site which seems to have some good information. It says you need to check for support with cpuid, then set bit9 of cr4. Also, you need to make sure that esp is paragraph (16-byte) aligned or an expcetion will occur. Hope some of that helps...

- Brandon

[FlashBurn]

OK, I fixed the problem now! The problem was that I save the state in the stack, but the addresse have to be a multiply of 16!

But I still don?t understand why Bochs doesn?t want to execute my code. Because when I don?t set the 9th bit in cr4 the fxsave command only save the mmx state and mmx support has Bochs!

One more question, is it possible that the fsave option also saves the mmx state if the cpu supports it? But the intel manuals say that if you not set the 9th bit of cr4 then the fxsave command will only save the state of the fpu and mmx!

[beyond infinity lazy]

(sooo...)

Have you compiled the bochs with --enable-sse and
--enable-mmx? It Might be helpful.

[Solar]

But I still don?t understand why Bochs doesn?t want to execute my code.

Because Bochs has been compiled without SSE support, as you said yourself in an earlier post...? ???

[FlashBurn]

Yeah, but in the intel manuals is written that if I don?t set the bit in cr4 that the command fsave will only save the mmx state! And my Bochs version has mmx support! But I will try to compile Bochs for myself with sse support so that I can go on!