starting first process

[unknown user]

hi. i'm writing an os called HakwareOS, and i have the pmode part done (mostly taken from OSD and mutilated for nasm), but i need to make the first process as the kernel so that i can run the next program (because, in posix standard, when it runs a program it fork() s and then copies the code into the new tss). unfortunately, i used shortcuts in my fork() and execve(), and so i didn't actually learn the correct format for a tsr, task gate, or tss. basically what i'm saying is, can anyone show me the struc used to create a tsr and what the values do? i was reading the i386 programmer's manual, but the wording is too confusing, and so i think that straight-out code (commented) would be best. all i need is the struc, and i can do the rest myself. thanks ^^;.

[Peter_Vigren]

hi. i'm writing an os called HakwareOS, and i have the pmode part done (mostly taken from OSD and mutilated for nasm), but i need to make the first process as the kernel so that i can run the next program (because, in posix standard, when it runs a program it fork() s and then copies the code into the new tss). unfortunately, i used shortcuts in my fork() and execve(), and so i didn't actually learn the correct format for a tsr, task gate, or tss. basically what i'm saying is, can anyone show me the struc used to create a tsr and what the values do? i was reading the i386 programmer's manual, but the wording is too confusing, and so i think that straight-out code (commented) would be best. all i need is the struc, and i can do the rest myself. thanks ^^;.

TSR? The Task Registry? All you have to do is to load the task selector with LTR Reg. E.g.:

Code: Select all

Mov Ax,SystemTaskSelector
Ltr Ax

The format of the task descriptor in the GDT is:

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SystemTaskSelector???equ???$-GlobalDescriptorTableBeginning

SystemTaskDescriptor:
???dw 103?????????; Limit/Length
???dw 0?????????; Base 0
???db 0?????????; Base 0
???db 10001001b??????; P=1, DPL=00, DT=0, Available 386 TSS (1,0,0,0,1001)
???db 01000000b??????; G=1, D=1, 0, AVL=0, 1111=F: Limit/Length (1,1,0,0,1111)
???db 0?????????; Base 0

The Base must point to the TSS and the limit must be at least 103 (104 bytes).

TSS structure:

Code: Select all

TaskSceleton:
Task_BackLink???dw???0,0

Task_Esp0???dd???0
Task_Ss0???dw???0,0

Task_Esp1???dd???0
Task_Ss1???dw???0,0

Task_Esp2???dd???0
Task_Ss2???dw???0,0

Task_Cr3???dd???0
Task_Eip???dd???0
Task_Eflags???dd???0
Task_Eax???dd???0
Task_Ecx???dd???0
Task_Edx???dd???0
Task_Ebx???dd???0
Task_Esp???dd???0
Task_Ebp???dd???0
Task_Esi???dd???0
Task_Edi???dd???0

Task_Es??????dw???0,0
Task_Cs??????dw???0,0
Task_Ss??????dw???0,0
Task_Ds??????dw???0,0
Task_Fs??????dw???0,0
Task_Gs??????dw???0,0

Task_LDT???dw???0,0
Task_Trap???dw???0
Task_IOMapBase???dw???0

Task_IOBitmap???times???128???db???0

Please, feel free to correct me if I am wrong.

I hope I gave you the answers you were looking for...

[unknown user]

thankyou!

[Peter_Vigren]

thankyou!

I'm glad if I can help. But I must warn ya, I myself have difficulties with this... however, the first process I seem to be able to set up... well, well...

[Pype.Clicker]

first thing ever: load a valid TSS descriptor into the Task Register. This TSS will not affect the current CPU state, but it will be mandatory to store the current context when you'll try to switch to another one.

second, if you want to make the current process run a user-mode segment, load a valid SS0/ESP0 pair in the current TSS. Note that it's unusual to do this as the task runs. You usually have either a kernel-started process that will only run in kernel mode or a user-started process that will use SS0/ESP0 for handling interrupts or system calls.

[unknown user]

i have it assembling. unfortunately, i can't get it to load code from the correct address when i boot up. i'm not sure where i should put the pointer to my code's label in the tss. does anyone know? at some point i'll attach my code so far so that people can see it.

[Pype.Clicker]

for the very first task (i.e. the one that correspond to the booted kernel, you simply have nothing to prepare : the eip pointer will be written by the CPU by the first time you JMP or CALL another task (as part of the state saving mechanism).

For other tasks, set the EIP where you'd like the thread to start. It can be the user process entry point (to be defined by the program loader) or some kernel function that will be in charge to prepare the address space and make things running.

In Clicker, the second presented approach is used. In m0bius, Tim starts executing at 0xdeadbeef, which is a conventionnal invalid (in kernel) address which triggers a page fault that the kernel handle by preparing the address space and starting the user threads.

[Tim]

But then again, I'm not using TSS switching. The 0xdeadbeef thing is used because the process that creates the new process doesn't have access to its memory (and so it can't load any code).

[unknown user]

i'm also a little confused as to what else i need to do with the tss, task selector, gdt, etc. before i ltr. i guess i'll read the manual again, since that's pretty much a function-based problem. perhaps i can call my label instead of doing a jmp far (in machine code, since the tut said that most assemblers optimize and would turn the jmp far into a jmp near, but i'm not sure if the "times 3 db 0eah, start32, 0x0000" would work in nasm). i tried doing a standard jmp, but it didn't work, so i tried the machine-code jmp far from the tut, but that didn't work either. the problem could be in any part of the code. i suppose i should zip my whole src dir and my compile tool package and put it online, so that someone could tell me what's wrong, while knowing about the other two modules. ^^;

[unknown user]

http://hakware.cjb.net/downloads/<---my kernel and tools. everything you need to build the hakwareOS kernel except dos (and maybe himem.sys).

[Tim]

If you ask me, don't bother with hardware TSS switching. Use software switching -- it's easier to understand, and better in the long term.

[beyond infinity lazy]

unknown user...

use either tss for hardware task switching and take into consideration that you need a tss-field for EACH process/thread in your kernel (and of course the apropriate descriptors in your global descriptor table,

or use software task switching, where you tell the computer everything which he does automatically and not really debugable in hardware task switching. It of course adds some layer of code to your isr-stubs, but this is a matter of programming once, debug it and then watch with a happy grin how smooth the tasks are switched.

Maybe, given the time, I'll compose a paper about software task switching along with some hints for nasm. I've some knowledge about programming for I do it to gain my living (or similar i don't know the exact idiom ...), but several nitty gritty is so obvious that not even experienced programmers would think about it.

stay safe

[beyond infinity lazy]

by the way: whats that for a programming language: tackle? Kinda basic dialect?

further, drop an eye to your idt.asm-code:
At this module's beginning, you have an instruction *jmp idt_end*

scrolling down this file, I'v discovered that you have string definitions prior to code. alas, this means, you send your cpu to string def hell instead to useable code. your cpu doesn't care. It executes the code you drop to it's muzzle anyway, but for it can't make sense out of it, it throws one exception after an other: Hardware exceptions, no java nor c++ exceptions! I suppose you move the string definitions to the beginning of this file, after the jmp-instruction, so that the label down under points to code.

hope this hint helps. Other possible bugs I won't search for cuz your file is a bit huuuuuge.

[Perica]

..

[tom1000000]

Hi,


IMHO hardware task switching is useless and should be avoided.

Why? Because it doesn't support multithreading.

Each time there's a hardware task switch, the CR3 (page directory base pointer) register is reloaded from the new TSS. This generally would invalidate almost all TLB entries.

If you have multiple threads in the same address space, you don't want to be reloading CR3 everytime you switch threads. It would cause many needless TLB lookups.