HW Port adresses and paged memory

[distantvoices]

I experiment and I wonder...

Now, I have mapped all adresses of memory area from 0x00000000 - 0x000fffff to 0xd0000000 - 0xd000fffff.

Despite this mapping, all the hard ware ports with adresses like 0x60, 0x64, 0x20 0xa0 are accessible as before. I 'm just curious for I tought, they would have to be mapped too. Or am I completely dumb and ignorant about hardware ports?

thank ya for illumination in this issue. I see it runs, but I want to know why. doesn't i386 architecture use memory mapped io?

[Pype.Clicker]

hey, dude! what are you trying to do, here ? paging I/O ports ?

ports are *not* memory locations. Despites many architecture (powerPC, sparcs, etc) uses memory-mapped IO, Intel processor have dedicated in <port>,a* and out <port>,a* instructions and I/O address space is totally distinct from memory address space (for instance, IO space is only 16 bits wide

So, whatever the memory mapping you set up with your pager, keyboard port will *always* be at 0x60.

[distantvoices]

Thanks for explanation gosh,

and NAY, I wouldna page hw-ports even in my weirdest dreams. I am not completely gone crazy *rofl*

I am spoiled by lowlevel hardware programming with microprocessors like pic16c74 (or similar) where you have to set input output masks to dedicated adresses in this small processors adress space prior to using them as input/output ports.

But that's what learning is good for. So I don't need to care about io-ports whilst using paging. this makes me happy

stay safe and thank ya, pype.