Do I need a TSS or LDT

[srg]

Hi
On a 32-bit pmode os with a flat memory model and paging, I understand that one method to handle the Segmentation of the x86 CPU is to have four 4GB (supervisor code, supervisor data, user code and user data) Segments, a GDT of course and an IDT, not forgetting call gates for API calls etc.

What I'm not sure about is what to do with the Task Register (do I create any TSS's?) or the LDTR (I don't want an LDT). Do I simply set these to 0?

Plus where do I asign the stack (to the data segements possibly?).

Thanks

[srg]

I guess I have answered my own questions

[Pype.Clicker]

a TSS is mandatory as soon as you want to have a user code at DPL3. this is mainly in order to have a SS0 and ESP0 that will be used by the CPU when an interrupt occurs and that a switch to mode 0 is necessary to handle it .