What is causing the following Error?

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gamingjam60
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What is causing the following Error?

Post by gamingjam60 »

When I am trying to start application cores then I am getting following error

Code: Select all

CPU Reset (CPU 3)
EAX=00000000 EBX=00000000 ECX=00000000 EDX=00060fb1
ESI=00000000 EDI=00000000 EBP=00000000 ESP=00000000
EIP=0000fff0 EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=1
ES =0000 00000000 0000ffff 00009300
CS =f000 ffff0000 0000ffff 00009b00
SS =0000 00000000 0000ffff 00009300
DS =0000 00000000 0000ffff 00009300
FS =0000 00000000 0000ffff 00009300
GS =0000 00000000 0000ffff 00009300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT=     00000000 0000ffff
IDT=     00000000 0000ffff
CR0=60000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000 
DR6=00000000ffff0ff0 DR7=0000000000000400
CCS=00000000 CCD=00000000 CCO=DYNAMIC
EFER=0000000000000000
FCW=037f FSW=0000 [ST=0] FTW=00 MXCSR=00001f80
FPR0=0000000000000000 0000 FPR1=0000000000000000 0000
FPR2=0000000000000000 0000 FPR3=0000000000000000 0000
FPR4=0000000000000000 0000 FPR5=0000000000000000 0000
FPR6=0000000000000000 0000 FPR7=0000000000000000 0000
XMM00=0000000000000000 0000000000000000 XMM01=0000000000000000 0000000000000000
XMM02=0000000000000000 0000000000000000 XMM03=0000000000000000 0000000000000000
XMM04=0000000000000000 0000000000000000 XMM05=0000000000000000 0000000000000000
XMM06=0000000000000000 0000000000000000 XMM07=0000000000000000 0000000000000000
Invalid read at addr 0xB0000000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0008000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0010000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0018000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0020000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0028000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0030000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0038000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0040000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0048000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0050000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0058000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0060000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0068000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0070000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0078000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0080000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0088000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0090000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB0098000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00A0000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00A8000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00B0000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00B8000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00C0000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00C8000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00D0000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00D8000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00E0000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00E8000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00F0000, size 2, region '(null)', reason: rejected
Invalid read at addr 0xB00F8000, size 2, region '(null)', reason: rejected
   584: v=03 e=0000 i=1 cpl=0 IP=0008:00000000000efb0a pc=00000000000efb0a SP=0010:0000000000000fc8 env->regs[R_EAX]=00000000000f6106
EAX=000f6106 EBX=000f3e0a ECX=00000000 EDX=00000cf9
ESI=00000000 EDI=00100000 EBP=00000000 ESP=00000fc8
EIP=000efb0a EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
CS =0008 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
DS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
FS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
GS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT=     000f6180 00000037
IDT=     000f61be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000 
DR6=00000000ffff0ff0 DR7=0000000000000400
CCS=000f61c8 CCD=00009e34 CCO=SUBL
EFER=0000000000000000
check_exception old: 0xffffffff new 0xd
   585: v=0d e=001a i=0 cpl=0 IP=0008:00000000000efb0a pc=00000000000efb0a SP=0010:0000000000000fc8 env->regs[R_EAX]=00000000000f6106
EAX=000f6106 EBX=000f3e0a ECX=00000000 EDX=00000cf9
ESI=00000000 EDI=00100000 EBP=00000000 ESP=00000fc8
EIP=000efb0a EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
CS =0008 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
DS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
FS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
GS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT=     000f6180 00000037
IDT=     000f61be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000 
DR6=00000000ffff0ff0 DR7=0000000000000400
CCS=000f61c8 CCD=00009e34 CCO=SUBL
EFER=0000000000000000
check_exception old: 0xd new 0xd
   586: v=08 e=0000 i=0 cpl=0 IP=0008:00000000000efb0a pc=00000000000efb0a SP=0010:0000000000000fc8 env->regs[R_EAX]=00000000000f6106
EAX=000f6106 EBX=000f3e0a ECX=00000000 EDX=00000cf9
ESI=00000000 EDI=00100000 EBP=00000000 ESP=00000fc8
EIP=000efb0a EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
CS =0008 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
DS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
FS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
GS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT=     000f6180 00000037
IDT=     000f61be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000 
DR6=00000000ffff0ff0 DR7=0000000000000400
CCS=000f61c8 CCD=00009e34 CCO=SUBL
EFER=0000000000000000
check_exception old: 0x8 new 0xd
Triple fault
Do not understand how it is happening

Code: Select all

Invalid read at addr 0xB0000000, size 2, region '(null)', reason: rejected
. . . .
Invalid read at addr 0xB00F8000, size 2, region '(null)', reason: rejected
Here first error: APIC Timer Interrupt

Code: Select all

584: v=03 e=0000 i=1 cpl=0 IP=0008:00000000000efb0a pc=00000000000efb0a SP=0010:0000000000000fc8 env->regs[R_EAX]=00000000000f6106
2nd error: General Protection Fault

Code: Select all

585: v=0d e=001a i=0 cpl=0 IP=0008:00000000000efb0a pc=00000000000efb0a SP=0010:0000000000000fc8 env->regs[R_EAX]=00000000000f6106
3rd Error: Double Fault

Code: Select all

586: v=08 e=0000 i=0 cpl=0 IP=0008:00000000000efb0a pc=00000000000efb0a SP=0010:0000000000000fc8 env->regs[R_EAX]=00000000000f6106
4th Error: Triple fault

bootstrap core works perfectly.

Code: Select all

void target_cpu_task(struct limine_smp_info *smp_info) {

    int core_id = (int) smp_info->lapic_id;

    uint8_t *stack_top = ap_stacks[core_id] + STACK_SIZE;

    // Set the stack pointer
    set_rsp((uint64_t) stack_top);
    
    asm volatile("cli");

    // Initialize GDT and TSS for this core
    init_gdt_tss_in_cpu(core_id);

    // Initialize interrupts for this core
    init_core_interrupt(core_id);

    // Initialize APIC for this 
    init_apic_interrupt();

    // Route IRQs to the current core
    uint32_t lapic_flags = (0 << 8) | (0 << 13) | (0 << 15);

    ioapic_route_irq(1, core_id, 33, lapic_flags);      // Route IRQ 1 to current LAPIC ID with vector 33
    ioapic_route_irq(2, core_id, 34, lapic_flags);      // Route IRQ 2 to current LAPIC ID with vector 34
    ioapic_route_irq(3, core_id, 35, lapic_flags);      // Route IRQ 3 to current LAPIC ID with vector 35
    ioapic_route_irq(4, core_id, 36, lapic_flags);      // Route IRQ 4 to current LAPIC ID with vector 36
    ioapic_route_irq(5, core_id, 37, lapic_flags);      // Route IRQ 5 to current LAPIC ID with vector 37
    ioapic_route_irq(6, core_id, 38, lapic_flags);      // Route IRQ 6 to current LAPIC ID with vector 38
    ioapic_route_irq(7, core_id, 39, lapic_flags);      // Route IRQ 7 to current LAPIC ID with vector 39
    ioapic_route_irq(8, core_id, 40, lapic_flags);      // Route IRQ 8 to current LAPIC ID with vector 40
    ioapic_route_irq(9, core_id, 41, lapic_flags);      // Route IRQ 9 to current LAPIC ID with vector 41
    ioapic_route_irq(10, core_id, 42, lapic_flags);     // Route IRQ 10 to current LAPIC ID with vector 42
    ioapic_route_irq(11, core_id, 43, lapic_flags);     // Route IRQ 11 to current LAPIC ID with vector 43
    ioapic_route_irq(12, core_id, 44, lapic_flags);     // Route IRQ 12 to current LAPIC ID with vector 44
    ioapic_route_irq(13, core_id, 45, lapic_flags);     // Route IRQ 13 to current LAPIC ID with vector 45
    ioapic_route_irq(14, core_id, 46, lapic_flags);     // Route IRQ 14 to current LAPIC ID with vector 46
    ioapic_route_irq(15, core_id, 47, lapic_flags);     // Route IRQ 15 to current LAPIC ID with vector 47
    ioapic_route_irq(16, core_id, 48, lapic_flags);     // Route IRQ 16 to current LAPIC ID with vector 48
    ioapic_route_irq(17, core_id, 49, lapic_flags);     // Route IRQ 17 to current LAPIC ID with vector 49
    ioapic_route_irq(18, core_id, 50, lapic_flags);     // Route IRQ 18 to current LAPIC ID with vector 50

    ioapic_route_irq(140, core_id, 172, lapic_flags);   // Route IRQ 140 to current LAPIC ID with vector 172
    ioapic_route_irq(141, core_id, 173, lapic_flags);   // Route IRQ 141 to current LAPIC ID with vector 173
    ioapic_route_irq(142, core_id, 174, lapic_flags);   // Route IRQ 142 to current LAPIC ID with vector 174

    init_apic_timer(100);
    initKeyboard();
    
    // Enable interrupts for this core
    asm volatile("sti");

    printf("[Info] CPU %d initialized!\n");
}

void start_bootstrap_cpu_core() {
    uint32_t bsp_lapic_id = smp_response->bsp_lapic_id;
    asm volatile("cli");
    init_acpi();
    parse_madt(madt);

    gdt_tss_init();
    init_bootstrap_interrupt(bsp_lapic_id);
    init_tsc();
    init_apic_interrupt();
   
    // Route IRQs to the bootstrap core
    uint32_t bsp_flags = (0 << 8) | (0 << 13) | (0 << 15);
    
    ioapic_route_irq(0, bsp_lapic_id, 32, bsp_flags);      // Route IRQ 1 to current LAPIC ID with vector 33
    ioapic_route_irq(1, bsp_lapic_id, 33, bsp_flags);      // Route IRQ 1 to current LAPIC ID with vector 33
    ioapic_route_irq(2, bsp_lapic_id, 34, bsp_flags);      // Route IRQ 2 to current LAPIC ID with vector 34
    ioapic_route_irq(3, bsp_lapic_id, 35, bsp_flags);      // Route IRQ 3 to current LAPIC ID with vector 35
    ioapic_route_irq(4, bsp_lapic_id, 36, bsp_flags);      // Route IRQ 4 to current LAPIC ID with vector 36
    ioapic_route_irq(5, bsp_lapic_id, 37, bsp_flags);      // Route IRQ 5 to current LAPIC ID with vector 37
    ioapic_route_irq(6, bsp_lapic_id, 38, bsp_flags);      // Route IRQ 6 to current LAPIC ID with vector 38
    ioapic_route_irq(7, bsp_lapic_id, 39, bsp_flags);      // Route IRQ 7 to current LAPIC ID with vector 39
    ioapic_route_irq(8, bsp_lapic_id, 40, bsp_flags);      // Route IRQ 8 to current LAPIC ID with vector 40
    ioapic_route_irq(9, bsp_lapic_id, 41, bsp_flags);      // Route IRQ 9 to current LAPIC ID with vector 41
    ioapic_route_irq(10, bsp_lapic_id, 42, bsp_flags);     // Route IRQ 10 to current LAPIC ID with vector 42
    ioapic_route_irq(11, bsp_lapic_id, 43, bsp_flags);     // Route IRQ 11 to current LAPIC ID with vector 43
    ioapic_route_irq(12, bsp_lapic_id, 44, bsp_flags);     // Route IRQ 12 to current LAPIC ID with vector 44
    ioapic_route_irq(13, bsp_lapic_id, 45, bsp_flags);     // Route IRQ 13 to current LAPIC ID with vector 45
    ioapic_route_irq(14, bsp_lapic_id, 46, bsp_flags);     // Route IRQ 14 to current LAPIC ID with vector 46
    ioapic_route_irq(15, bsp_lapic_id, 47, bsp_flags);     // Route IRQ 15 to current LAPIC ID with vector 47
    ioapic_route_irq(16, bsp_lapic_id, 48, bsp_flags);     // Route IRQ 16 to current LAPIC ID with vector 48
    ioapic_route_irq(17, bsp_lapic_id, 49, bsp_flags);     // Route IRQ 17 to current LAPIC ID with vector 49
    ioapic_route_irq(18, bsp_lapic_id, 50, bsp_flags);     // Route IRQ 18 to current LAPIC ID with vector 50

    ioapic_route_irq(140, bsp_lapic_id, 172, bsp_flags);   // Route IRQ 140 to current LAPIC ID with vector 172
    ioapic_route_irq(141, bsp_lapic_id, 173, bsp_flags);   // Route IRQ 141 to current LAPIC ID with vector 173
    ioapic_route_irq(142, bsp_lapic_id, 174, bsp_flags);   // Route IRQ 142 to current LAPIC ID with vector 174

    init_apic_timer(100);
    initKeyboard();

    asm volatile("sti");
    printf("[Info] Bootstrap CPU initialized...\n");
}



void start_secondary_cpu_cores(int start_id, int end_id) {
    for (int core = start_id; core < end_id; core++) {
        struct limine_smp_info *smp_info = smp_response->cpus[core];

        // passing sm_info as argument which will accept as input by target_cpu_task
        smp_info->extra_argument = (uint64_t)smp_info;

        // Set function to execute on the AP
        smp_info->goto_address = (limine_goto_address) target_cpu_task;

        // Short delay to let APs start (only for debugging)
        for (volatile int i = 0; i < 1000000; i++);
    }
}
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Octocontrabass
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Posts: 5758
Joined: Mon Mar 25, 2013 7:01 pm

Re: What is causing the following Error?

Post by Octocontrabass »

gamingjam60 wrote: ↑Sun Apr 20, 2025 11:42 am

Code: Select all

CPU Reset (CPU 3)
CS =f000 ffff0000 0000ffff 00009b00
This AP is resetting and jumping to the BIOS. The rest of the problems you see in the log are caused by this AP trying to execute BIOS code. Why is this AP resetting? Limine has already initialized the APs for you, so you shouldn't reset them.
gamingjam60 wrote: ↑Sun Apr 20, 2025 11:42 am

Code: Select all

    // Set the stack pointer
    set_rsp((uint64_t) stack_top);
You can't set the stack pointer in the middle of a function like this. You don't need to set the stack pointer because Limine has already done it for you. If you want to switch to a different stack anyway, you need to do a context switch, just like you would when you switch tasks.
gamingjam60 wrote: ↑Sun Apr 20, 2025 11:42 am

Code: Select all

    ioapic_route_irq(1, core_id, 33, lapic_flags);      // Route IRQ 1 to current LAPIC ID with vector 33
...
    ioapic_route_irq(18, core_id, 50, lapic_flags);     // Route IRQ 18 to current LAPIC ID with vector 50
Why does each AP direct all IRQs to itself when it starts?
gamingjam60 wrote: ↑Sun Apr 20, 2025 11:42 am

Code: Select all

    initKeyboard();
Why does each AP initialize the keyboard?
gamingjam60 wrote: ↑Sun Apr 20, 2025 11:42 am

Code: Select all

    ioapic_route_irq(140, bsp_lapic_id, 172, bsp_flags);   // Route IRQ 140 to current LAPIC ID with vector 172
    ioapic_route_irq(141, bsp_lapic_id, 173, bsp_flags);   // Route IRQ 141 to current LAPIC ID with vector 173
    ioapic_route_irq(142, bsp_lapic_id, 174, bsp_flags);   // Route IRQ 142 to current LAPIC ID with vector 174
Do these IRQs really exist in the hardware you're using?
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gamingjam60
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Re: What is causing the following Error?

Post by gamingjam60 »

I found the solution
Here Limine starts paging only for bootstrap cpu so I need to set cr3 address for all other application core so it was showing cr3=0 and causing memory error.
Now I have set cr3 of all application cpu with bootstrap cpu cr3 value.
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