CPU_Registers_x86#Control_Registers

[lambdart]

The wiki page should specific that the LMSW instruction can indeed modify the cr0 register,
but only the 4 lower bits will be modified which contains the PE, MP, EM, and TS flags.

From Intel's Manual (Volume 2A):

LMSW — Load Machine Status Word

Description

Loads the source operand into the machine status word, bits 0 through 15 of
register CR0. The source operand can be a 16-bit general-purpose register or a
memory location. Only the low-order 4 bits of the source operand (which contains
the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE,
and ET flags of CR0 are not affected. The operand-size attribute has no effect
on this instruction.

If the PE flag of the source operand (bit 0) is set to 1, the instruction causes
the processor to switch to protected mode. While in protected mode, the LMSW
instruction cannot be used to clear the PE flag and force a switch back to
real-address mode.

...

Operation

CR0[0:3] := SRC[0:3];

Flags Affected

None

[iansjack]

So, edit the wiki page. That's what wikis are for.

[lambdart]

I don't have permission.

[iansjack]

viewtopic.php?t=677

[lambdart]

Thanks, will do.