[SOLVED] Division exception triggering ISR 6?

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torii
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[SOLVED] Division exception triggering ISR 6?

Post by torii »

I have been working on a new kernel recently, and noticed some strange behaviour. I noticed that my exception handler was not displaying the correct error message on a division-by-zero error. After running the kernel through GDB, i found that the ISR being called was not zero, as I expected based on the wiki, but instead 6.

Is it possible that I have implemented something incorrectly, or is this just how things work and im misreading the wiki?

Relevant Information:
- Interrupts being tested with line `int i = 1/0`
- Compiler: GCC
- VM: Qemu
- Debugger: GDB
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interrupts_being_weird.png
Last edited by torii on Mon Feb 03, 2025 12:36 pm, edited 1 time in total.
Octocontrabass
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Re: Division exception triggering ISR 6?

Post by Octocontrabass »

torii wrote: Sun Feb 02, 2025 6:06 pmint i = 1/0
In C, division by zero is undefined behavior. That means your compiler is free to generate whatever code it wants - including code that causes #UD (interrupt 6) when you were expecting #DE (interrupt 0).

If you want to see #DE, you can use inline assembly:

Code: Select all

asm( "div %ah" );
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JackScott
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Re: Division exception triggering ISR 6?

Post by JackScott »

I just tested this in my kernel. I also received interrupt #6. Note I had to add a line of code using i for something afterwards, otherwise my particular combination of GCC and CFLAGS would optimise it out.
torii
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Re: Division exception triggering ISR 6?

Post by torii »

Octocontrabass wrote: Sun Feb 02, 2025 6:15 pm If you want to see #DE, you can use inline assembly:

Code: Select all

asm( "div %ah" );
Seems undefined behaviour was the problem - I hadn't even considered that as a possibility. Replacing the C code with inline assembly to trigger the interrupt resulted in #DE as expected.

Thanks for the help!
Writing bad code since 2019
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