MOSI- SPI

[Octocontrabass]

If it's not SMI, I don't know what it could be. You'll have to ask Intel, unfortunately.

[ravi]

ok Thanks, i had asked them months ago,

[ravi]

Hello Octocontrabass

i am not able to get any interrupts from EHL PSE SPI,, i cleared the required bits in IMR register set to (0x2f) to enable RX FIFO full and set the threshold accordingly, but when the conditions are met ISR bit 4 is not set, but RISR reflects the status,

there is option to enable sideband interrupts for PSE SPI in the slim boot loader should i enable it?

thanks
Ravi

[Octocontrabass]

i cleared the required bits in IMR register set to (0x2f) to enable RX FIFO full

I think you need to set bits to enable interrupts. Try 0x10.

there is option to enable sideband interrupts for PSE SPI in the slim boot loader should i enable it?

I think that might be for using PIC/IOAPIC instead of MSI?

[ravi]

Hello Octocontrabass

Yeah , i need to set the bits, i realized it as soon as i posted this question.

i had to enable sideband interrupts through Apic

thanks
Ravi

[ravi]

Hello Octocontrabass,

i am trying to set up DMA for PSE SPI, with PSE DMA controller,

i am able to set it up for TX,(i.e to put the data into SPI FIFO, from memory), in both direct method and linked list method, but some how unable to set up RX DMA using linked list method(but direct method works),, Not sure why,,

following is what i am doing
Set up LL by set
LL.DAR = Address of memory, LL.SAR = PSE SPI data register, LL.LLP =0, ll.CL0 = 0x18200412, LL.HL0 =E0000016

Set the PSE SPI DMA control register to 1(i.e DMA receive enable, Set PSE SPI DMA LR to 0 , set DMA REG access register to 0 (selecting channel 0), DMA control register to 0x101, xbar select reg to 0x99, CFG LO to TX and RX burst aligned, CFG HI to SRC id as 1 and dest id 0 and bit 30 as1, CTL L0 as 0x18000000 indicating list transfer, CTL HI to E000FFFF and DMA config register to enable and enable the channel ,, nothing happens

note: instead of using LL if i set the registers with same above mentioned value in the registers directly(direct method ), then transfer happens ,, the same things i have done for TX using LL it works,,, not sure for RX LL why its not working

thanks

[Octocontrabass]

Does anything happen at all? Do you receive any interrupts? Do any status registers change? Does the DMA controller write anything to SSTAT or DSTAT in your linked list?

[ravi]

no nothing happens at all .... all the status registers are 0,,

I think DMA controller should switch to linked list mode if it has valid pointer in LLP and CTL L0 indicates it (0x18000000), but for some reason i believe its not seeing this and loading its registers from the list,,, but not sure,, if i do similar thing with Tx everything works perfectly

Thanks
Ravi

[ravi]

LLP0 register in which i set linked list address gets zeroed after i enable the channel

[ravi]

when i enable channel following happens when i enable the channel


1) LLP0 register in which i set linked list address gets zeroed
2) CTL LO gets zeroed
3) CTL HI gets zeroed
4) Error gets set in reg offset 0x2e0 , and also bit 16 gets set at DMA error register 0ffset 0x1404,, indicating Peripheral BAR remap error

Note:- Keeping all the above setting, only change the mode to direct mode i.e load the same values into SAR/DAR register etc works,, this kind of indicates that SAR and DAR address are at least right

Note: The same method i used to tx it works fine, indicating that LL alignment and format is fine, since i am using the same LL

[Octocontrabass]

Unfortunately I don't know what causes a BAR remap error. Is it explained somewhere?

What values are in SSTATAR and DSTATAR?

[ravi]

NP, thanks for giving a thought

no i tried to google it , no luck, put a IPS ticket,, not sure when i will get reply

SSTATAR and DSTATAR are zero's

Thanks
Ravi

[ravi]

Hello Octocontrabass,


PSE DMA interrupts are confusing me there is no documentation,

if you are aware of it can give me a overview of it

consider the scenario, i want the DMA to transfer the data from SPI buffer to main memory and generate an interrupt after that

i know i have to Enable all the interrupts in the Channel specific control register,,, but after i am not clear how to un mask and read this interrupt

Thanks
Ravi

[ravi]

i got it now working thanks